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| HD6433044 Datasheet, PDF (329/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer | |||
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Bit 2âMaster Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4.
Bit 2
EB4
0
1
Description
TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4 operates as
a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
TIOCB4 is enabled for output according to TIOR4 and TFCR settings
(Initial value)
Bit 1âMaster Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.
Bit 1
EA4
0
1
Description
TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4
operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
TIOCA4 is enabled for output according to TIOR4, TMDR, and
TFCR settings
(Initial value)
Bit 0âMaster Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.
Bit 0
EA3
Description
0
TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3
operates as a generic input/output pin).
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
1
TIOCA3 is enabled for output according to TIOR3, TMDR, and
TFCR settings
(Initial value)
317
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