HD6433044 Datasheet, PDF (646/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

External Clock: The external clock frequency should be equal to the system clock frequency
(ø) when not divided by the on-chip frequency divider. Table 19-3, figures 19-6 and 19-7
indicate the clock timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by
the on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to
external devices after the external clock settling time (t_DEXT) has passed after the clock input.
The system must remain reset with the reset signal low during t_DEXT, while the clock output is
unstable.
Table 19-3 Clock Timing
V_CC =
2.7 V to 5.5 V
Item
Symbol Min Max
External clock input t_EXL
40
—
low pulse width
External clock input t_EXH
40
—
high pulse width
External clock rise t_EXr
—
10
time
External clock fall t_EXf
—
10
time
Clock low pulse
t_CL
width
0.4
0.6
80
—
Clock high pulse
t_CH
width
0.4
0.6
80
—
External clock
output settling
delay time
t_DEXT* 500
—
Note: * t_DEXT includes 10 t_cyc of RES (t_RESW).
V_CC = 5.0 V ± 10%
Min
Max
Unit Test Conditions
20
—
ns Figure 19-6
20
—
ns
—
5
ns
—
5
ns
0.4
0.6
80
—
0.4
0.6
80
—
500
—
t_cyc ø ≥ 5 MHz Figure
ns ø < 5 MHz ^21-7
t_cyc ø ≥ 5 MHz
ns ø < 5 MHz
µs Figure 19-7
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