HD6433044 Datasheet, PDF (756/867 Pages) Hitachi Semiconductor – Hitachi Single-Chip Microcomputer

DTCR0A—Data Transfer Control Register 0A
• Short address mode
H'27
DMAC0
Bit
Initial value
Read/Write
7
DTE
0
R/W
6
DTSZ
0
R/W
5
DTID
0
R/W
4
RPE
0
R/W
3
DTIE
0
R/W
2
DTS2
0
R/W
1
DTS1
0
R/W
0
DTS0
0
R/W
Data transfer select
Bit 2 Bit 1 Bit 0
DTS2 DTS1 DTS0 Data Transfer Activation Source
0
0
0 Compare match/input capture A interrupt from ITU channel 0
1 Compare match/input capture A interrupt from ITU channel 1
1
0 Compare match/input capture A interrupt from ITU channel 2
1 Compare match/input capture A interrupt from ITU channel 3
1
0
0 SCI0 transmit-data-empty interrupt
1 SCI0 receive-data-full interrupt
1
0 Transfer in full address mode (channel A)
1 Transfer in full address mode (channel A)
Data transfer interrupt enable
0 Interrupt requested by DTE bit is disabled
1 Interrupt requested by DTE bit is enabled
Repeat enable
RPE DTIE Description
0
0 I/O mode
1
1
0 Repeat mode
1 Idle mode
Data transfer increment/decrement
0 Incremented: If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
1 Decremented: If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
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