XC3S100E_06 Datasheet, PDF (99/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
Intelligent
V
Download Host
Configuration
Memory
Source
• Internal memory
• Disk drive
• Over network
• Over RF link
VCC
CLOCK
SERIAL_OUT
PROG_B
DONE
INIT_B
GND
• Microcontroller
• Processor
• Tester
• Computer
+1.2V
P
Slave
Serial
Mode
‘1’
‘1’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2
M1
M0
Spartan-3E
CCLK _FPGA
DIN
DOUT
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
V
V
+2.5V
+2.5V
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
Figure 63: Slave Serial Configuration
DS312-2_54_022305
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
P Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
Voltage Compatibility
V _{Most Slave Serial interface signals are within the}
FPGA’s I/O Bank 2, supplied by the VCCO_2 supply input.
The VCCO_2 voltage can be 3.3V, 2.5V, or 1.8V to match
the requirements of the external host, ideally 2.5V. Using
3.3V or 1.8V requires additional design considerations as
the DONE and PROG_B pins are powered by the FPGA’s
2.5V V_CCAUX supply. See XAPP453: The 3.3V Configura-
tion of Spartan-3 FPGAs for additional information.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 64. Use Slave Serial mode
(M[2:0] = <1:1:1>) for all FPGAs in the daisy-chain. After
the lead FPGA is filled with its configuration data, the lead
FPGA passes configuration data via its DOUT output pin to
the next FPGA on the falling CCLK edge.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
99
Product Specification