XC3S100E_06 Datasheet, PDF (89/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 58: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name FPGA Direction
Description
During Configuration
After Configuration
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active
Low. Goes Low at start of
configuration during the
Initialization memory clearing
process. Released at the end of
memory clearing, when the mode
select pins are sampled. In
daisy-chain applications, this signal
requires an external 4.7 kΩ pull-up
resistor to VCCO_2.
Active during configuration. If CRC
error detected during
configuration, FPGA drives
INIT_B Low.
User I/O. If unused in the
application, drive INIT_B
High.
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
Low indicates that the FPGA is not
yet configured.
Pulled High via external
pull-up. When High,
indicates that the FPGA is
successfully configured.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer,
forces the FPGA to restart its
configuration process by clearing
configuration memory and
resetting the DONE and INIT_B
pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving externally
with a 3.3V output, use an
open-drain or open-collector driver
or use a current limiting series
resistor.
Must be High to allow
configuration to start.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
Voltage Compatibility
V _{The FPGA’s parallel Flash interface signals are within}
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage. Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
Power-On Precautions if PROM Supply is Last in
Sequence
Like SPI Flash PROMs, parallel Flash PROMs typically
require some amount of internal initialization time when the
supply voltage reaches its minimum value.
The PROM supply voltage also connects to the FPGA’s
VCCO_2 supply input. In many systems, the PROM supply
feeding the FPGA’s VCCO_2 input is valid before the
FPGA’s other V_CCINT and V_CCAUX supplies, and conse-
quently, there is no issue. However, if the PROM supply is
last in the sequence, a potential race occurs between the
FPGA and the parallel Flash PROM. See Power-On Pre-
cautions if 3.3V Supply is Last in Sequence for a similar
description of the issue for SPI Flash PROMs.
Supported Parallel NOR Flash PROM Densities
Table 59 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash den-
sity is specified in bits but addressed as bytes. The FPGA
presents up to 24 address lines during configuration but not
all are required for single FPGA applications. Table 59
shows the minimum required number of address lines
between the FPGA and parallel Flash PROM. The actual
number of address line required depends on the density of
the attached parallel Flash PROM.
A multiple-FPGA daisy-chained application requires a paral-
lel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-density
parallel Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the parallel Flash
PROM can also contain the application code for a MicroBlaze
RISC processor core implemented within the Spartan-3E
FPGA. After configuration, the MicroBlaze processor can
execute directly from external Flash or can copy the code to
other, faster system memory before executing the code.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
89
Product Specification