XC3S100E_06 Datasheet, PDF (33/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
WE
D
WCLK
A0
A1
A2
A3
DPRA0
DPRA1
DPRA2
DPRA3
RAM16X1D
SPO
DPO
DS312-2_42_021305
Figure 27: Dual-Port RAM Component
Table 18: Dual-Port RAM Function
Inputs
Outputs
WE (mode) WCLK
D
SPO
DPO
0 (read)
X
X
data_a data_d
1 (read)
0
X
data_a data_d
1 (read)
1
X
data_a data_d
1 (write)
↑
D
D
data_d
1 (read)
↓
X
data_a data_d
Notes:
1. data_a = word addressed by bits A3-A0.
2. data_d = word addressed by bits DPRA3-DPRA0.
Table 19: Distributed RAM Signals
Signal
Description
WCLK
The clock is used for synchronous
writes. The data and the address input
pins have setup times referenced to the
WCLK pin. Active on the positive edge
by default with built-in programmable
polarity.
WE
The enable pin affects the write
functionality of the port. An inactive
Write Enable prevents any writing to
memory cells. An active Write Enable
causes the clock edge to write the data
input signal to the memory location
pointed to by the address inputs. Active
High by default with built-in
programmable polarity.
Table 19: Distributed RAM Signals (Continued)
Signal
Description
A0, A1, A2, A3
(A4, A5)
The address inputs select the memory
cells for read or write. The width of the
port determines the required address
inputs.
D
The data input provides the new data
value to be written into the RAM.
O, SPO, and
DPO
The data output O on single-port RAM
or the SPO and DPO outputs on
dual-port RAM reflects the contents of
the memory cells referenced by the
address inputs. Following an active
write clock edge, the data out (O or
SPO) reflects the newly written data.
The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
for RAM is all zeros. If the WE is held Low, the element can
be considered a ROM. The ROM function is possible even
in the SLICEL.
The global write enable signal, GWE, is asserted automati-
cally at the end of device configuration to enable all writable
elements. The GWE signal guarantees that the initialized
distributed RAM contents are not disturbed during the con-
figuration process.
The distributed RAM is useful for smaller amounts of mem-
ory. Larger memory requirements can use the dedicated
18Kbit RAM blocks (see Block RAM).
For more information on distributed RAM, see XAPP464:
Using Look-Up Tables as Distributed RAM in Spartan-3
FPGAs.
Shift Registers
It is possible to program each SLICEM LUT as a 16-bit shift
register (see Figure 28). Used in this way, each LUT can
delay serial data anywhere from 1 to 16 clock cycles without
using any of the dedicated flip-flops. The resulting program-
mable delays can be used to balance the timing of data
pipelines.
The SLICEM LUTs cascade from the G-LUT to the F-LUT
through the DIFMUX (see Figure 15). SHIFTIN and
SHIFTOUT lines cascade a SLICEM to the SLICEM below
to form larger shift registers. The four SLICEM LUTs of a
single CLB can be combined to produce delays up to 64
clock cycles. It is also possible to combine shift registers
across more than one CLB.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
33
Product Specification