XC3S100E_06 Datasheet, PDF (65/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Horizontal and
Vertical Long Lines
(horizontal channel
shown as an example)
Figure 49: Array of Interconnect Tiles in Spartan-3E FPGA
24
DS312_09_020905
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
6
6
6
6
6
DS312-2_10_022305
Horizontal and
8
Vertical Hex Lines
(horizontal channel
shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Horizontal and
Vertical Double
Lines
(horizontal channel
shown as an example)
8
CLB
CLB
CLB
DS312-2_15_022305
Figure 50: Interconnect Types between Two Adjacent Interconnect Tiles
DS312-2_11_020905
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
65
Product Specification