XC3S100E_06 Datasheet, PDF (62/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Left-/Right-Half BUFGMUX
CLK Switch
Matrix
BUFGMUX
S
I0 _{0 O}
I1 ₁
I0 _{0 O}
I1 ₁
S
Top/Bottom (Global) BUFGMUX
CLK Switch
Matrix
BUFGMUX
S
I0 _{0 O}
I1 ₁
I0 _{0 O}
I1 ₁
S
LHCLK or
RHCLK input
Double Line
DCM output*
*(XC3S1200E and
XC3S1600E only)
1st GCLK pin
1st DCM output
Double Line
2nd DCM output
2nd GCLK pin
DS312-2_16_110706
Figure 46: Clock Switch Matrix to BUFGMUX Pair Connectivity
Quadrant Clock Routing
The clock routing within the FPGA is quadrant-based, as
shown in Figure 45. Each clock quadrant supports eight
total clock signals, labeled ‘A’ through ‘H’ in Table 41 and
Figure 47. The clock source for an individual clock line orig-
inates either from a global BUFGMUX element along the
top and bottom edges or from a BUFGMUX element along
the associated edge, as shown in Figure 47. The clock lines
feed the synchronous resource elements (CLBs, IOBs,
block RAM, multipliers, and DCMs) within the quadrant.
The four quadrants of the device are:
• Top Right (TR)
• Bottom Right (BR)
• Bottom Left (BL)
• Top Left (TL)
Note that the quadrant clock notation (TR, BR, BL, TL) is
separate from that used for similar IOB placement con-
straints.
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DS312-2 (v3.4) November 9, 2006
Product Specification