XC3S100E_06 Datasheet, PDF (67/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Configuration
Differences from Spartan-3 FPGAs
In general, Spartan-3E FPGA configuration modes are a
superset to those available in Spartan-3 FPGAs. Two new
modes added in Spartan-3E FPGAs provide a glue-less
configuration interface to industry-standard parallel NOR
Flash and SPI serial Flash memories. Unlike Spartan-3
FPGAs, nearly all of the Spartan-3E configuration pins
become available as user I/Os after configuration.
Configuration Process
The function of a Spartan-3E FPGA is defined by loading
application-specific configuration data into the FPGA’s
internal, reprogrammable CMOS configuration latches
(CCLs), similar to the way a microprocessor’s function is
defined by its application program. For FPGAs, this configu-
ration process uses a subset of the device pins, some of
which are dedicated to configuration; other pins are merely
borrowed and returned to the application as general-pur-
pose user I/Os after configuration completes.
Spartan-3E FPGAs offer several configuration options to
minimize the impact of configuration on the overall system
design. In some configuration modes, the FPGA generates
a clock and loads itself from an external memory source,
either serially or via a byte-wide data path. Alternatively, an
external host such as a microprocessor downloads the
FPGA’s configuration data using a simple synchronous
serial interface or via a byte-wide peripheral-style interface.
Furthermore, multiple-FPGA designs share a single config-
uration memory source, creating a structure called a daisy
chain.
Three FPGA pins—M2, M1, and M0—select the desired
configuration mode. The mode pin settings appear in
Table 43. The mode pin values are sampled during the start
of configuration when the FPGA’s INIT_B output goes High.
After the FPGA completes configuration, the mode pins are
available as user I/Os.
Table 43: Spartan-3E Configuration Mode Options and Pin Settings
Master
Serial
SPI
BPI
Slave Parallel Slave Serial
JTAG
M[2:0] mode pin
settings
<0:0:0>
<0:0:1>
<0:1:0>=Up
<0:1:1>=Down
<1:1:0>
<1:1:1>
<1:0:1>
Data width
Serial
Serial
Byte-wide
Byte-wide
Serial
Serial
Configuration memory
source
Xilinx
Platform
Flash
Industry-standard
SPI serial Flash
Industry-standard
parallel NOR
Flash or Xilinx
parallel Platform
Flash
Any source via
microcontroller,
CPU, Xilinx
parallel
Platform Flash,
etc.
Any source via
microcontroller,
CPU, Xilinx
Platform Flash,
etc.
Any source via
microcontroller,
CPU, System
ACE™ CF, etc.
Clock source
Internal
oscillator
Internal oscillator Internal oscillator External clock
on CCLK pin
External clock
on CCLK pin
External clock
on TCK pin
Total I/O pins
borrowed during
8
13
46
21
8
0
configuration
Configuration mode
for downstream
daisy-chained FPGAs
Slave Serial
Slave Serial
Slave Parallel
Slave Parallel or
Memory
Mapped
Slave Serial
JTAG
Stand-alone FPGA
applications (no
external download
9
9
host)
Possible using
Possible using
9
XCFxxP Platform XCFxxP Platform
Flash, which
Flash, which
optionally
optionally
generates CCLK generates CCLK
Uses low-cost,
industry-standard
Flash
9
9
Supports optional
MultiBoot,
9
multi-configuration
mode
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
67
Product Specification