XC3S100E_06 Datasheet, PDF (54/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Accommodating Input Frequencies Beyond Spec-
ified Maximums
If the CLKIN input frequency exceeds the maximum permit-
ted, divide it down to an acceptable value using the
CLKIN_DIVIDE_BY_2 attribute. When this attribute is set to
“TRUE”, the CLKIN frequency is divided by a factor of two
as it enters the DCM. In addition, the CLKIN_DIVIDE_BY_2
option produces a 50% duty-cycle on the input clock,
although at half the CLKIN frequency.
Quadrant and Half-Period Phase Shift Outputs
In addition to CLK0 for zero-phase alignment to the CLKIN
signal, the DLL also provides the CLK90, CLK180, and
CLK270 outputs for 90°, 180°, and 270° phase-shifted sig-
nals, respectively. These signals are described in Table 28,
page 49 and their relative timing is shown in Figure 43. For
control in finer increments than 90°, see Phase Shifter
(PS).
Phase:
0^o 90^o 180^o 270^o 0^o 90^o 180^o 270^o 0^o
Input Signal (40%/60% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle Corrected
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
DS099-2_10_101105
Figure 43: Characteristics of the DLL Clock Outputs
Basic Frequency Synthesis Outputs
The DLL component provides basic options for frequency
multiplication and division in addition to the more flexible
synthesis capability of the DFS component, described in a
later section. These operations result in output clock signals
with frequencies that are either a fraction (for division) or a
multiple (for multiplication) of the incoming clock frequency.
The CLK2X output produces an in-phase signal that is twice
the frequency of CLKIN. The CLK2X180 output also dou-
bles the frequency, but is 180° out-of-phase with respect to
CLKIN. The CLKDIV output generates a clock frequency
that is a predetermined fraction of the CLKIN frequency.
The CLKDV_DIVIDE attribute determines the factor used to
divide the CLKIN frequency. The attribute can be set to var-
ious values as described in Table 29. The basic frequency
synthesis outputs are described in Table 28.
Duty Cycle Correction of DLL Clock Outputs
The DLL output signals exhibit a 50% duty cycle, even if the
incoming CLKIN signal has a different duty cycle. Fifty-per-
cent duty cycle means that the High and Low times of each
clock cycle are equal.
DLL Performance Differences Between Steppings
As indicated in Digital Clock Manager (DCM) Timing
(Module 3), the Stepping 1 revision silicon supports higher
maximum input and output frequencies. Stepping 1 devices
are backwards compatible with Stepping 0 devices.
Digital Frequency Synthesizer (DFS)
The DFS unit generates clock signals where the output fre-
quency is a product of the CLKIN input clock frequency and
a ratio of two user-specified integers. The two dedicated
outputs from the DFS unit, CLKFX and CLKFX180, are
defined in Table 33.
Table 33: DFS Signals
Signal Direction
Description
CLKFX
Output
Multiplies the CLKIN frequency
by the attribute-value ratio
(CLKFX_MULTIPLY/
CLKFX_DIVIDE) to generate a
clock signal with a new target
frequency.
CLKFX180 Output
Generates a clock signal with
the same frequency as CLKFX,
but shifted 180° out-of-phase.
The signal at the CLKFX180 output is essentially an inver-
sion of the CLKFX signal. These two outputs always exhibit
a 50% duty cycle, even when the CLKIN signal does not.
The DFS clock outputs are active coincident with the seven
DLL outputs and their output phase is controlled by the
Phase Shifter unit (PS).
The output frequency (f_CLKFX) of the DFS is a function of the
incoming clock frequency (f_CLKIN) and two integer
attributes, as follows.
f_CLKFX
=
f_CLKIN •
⎛
⎝
C_-----LC_---K_-L---F_-K---X_-F---__-X--M_{--_---D-}U_---I-L_-V---T_--I-I_-D-P_---E-L_---Y_{---⎠⎞}
Eq. 1
The CLKFX_MULTIPLY attribute is an integer ranging from
2 to 32, inclusive, and forms the numerator in Equation 1.
54
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification