XC3S100E_06 Datasheet, PDF (219/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Pinout Descriptions
Table 151: FG400 Package Pinout (Continued)
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
VCCAUX VCCAUX
D11 VCCAUX
VCCAUX VCCAUX
H12 VCCAUX
VCCAUX VCCAUX
J7 VCCAUX
VCCAUX VCCAUX
K4 VCCAUX
VCCAUX VCCAUX
L17 VCCAUX
VCCAUX VCCAUX
M14 VCCAUX
VCCAUX VCCAUX
N9 VCCAUX
VCCAUX VCCAUX
U10 VCCAUX
VCCINT VCCINT
H9 VCCINT
VCCINT VCCINT
H11 VCCINT
VCCINT VCCINT
H13 VCCINT
VCCINT VCCINT
J8 VCCINT
VCCINT VCCINT
J10 VCCINT
Table 151: FG400 Package Pinout (Continued)
Bank
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
Type
VCCINT VCCINT
J12 VCCINT
VCCINT VCCINT
K9 VCCINT
VCCINT VCCINT
K11 VCCINT
VCCINT VCCINT
L10 VCCINT
VCCINT VCCINT
L12 VCCINT
VCCINT VCCINT
M9 VCCINT
VCCINT VCCINT
M11 VCCINT
VCCINT VCCINT
M13 VCCINT
VCCINT VCCINT
N8 VCCINT
VCCINT VCCINT
N10 VCCINT
VCCINT VCCINT
N12 VCCINT
User I/Os by Bank
Table 152 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG400 pack-
age.
Table 152: User I/Os Per Bank for the XC3S1200E and XC3S1600E in the FG400 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
78
43
20
1
6
Right
1
74
35
12
21
6
Bottom
2
78
30
18
24
6
Left
3
74
48
12
0
6
TOTAL
304
156
62
46
24
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
219
Product Specification