XC3S100E_06 Datasheet, PDF (53/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Every FPGA input provides a possible DCM clock input, but
the path is not temperature and voltage compensated like
the GCLKs. Alternatively, clock signals within the FPGA
optionally provide a DCM clock input via a Global Clock
Multiplexer Buffer (BUFGMUX). The global clock net con-
nects directly to the CLKIN input. The internal and external
connections are shown in Figure 42a and Figure 42c,
respectively.
DLL Clock Output and Feedback Connections
As many as four of the nine DCM clock outputs can simulta-
neously drive four of the BUFGMUX buffers on the same die
edge. All DCM clock outputs can simultaneously drive gen-
eral routing resources, including interconnect leading to
OBUF buffers.
The feedback loop is essential for DLL operation. Either the
CLK0 or CLK2X outputs feed back to the CLKFB input via a
BUFGMUX global buffer to eliminate the clock distribution
delay. The specific BUFGMUX buffer used to feed back the
CLK0 or CLK2X signal is ideally one of the BUFGMUX buff-
ers associated with a specific DCM, as shown in Table 30,
Table 31, and Table 32.
The feedback path also phase-aligns the other seven DLL
outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,
or CLK2X180. The CLK_FEEDBACK attribute value must
agree with the physical feedback connection. Use “1X” for
CLK0 feedback and “2X” for CLK2X feedback. If the DFS
unit is used stand-alone, without the DLL, then no feedback
is required and set the CLK_FEEDBACK attribute to
“NONE”.
Two basic cases determine how to connect the DLL clock
outputs and feedback connections: on-chip synchronization
and off-chip synchronization, which are illustrated in
Figure 42a through Figure 42d.
In the on-chip synchronization case in Figure 42a and
Figure 42b, it is possible to connect any of the DLL’s seven
output clock signals through general routing resources to
the FPGA’s internal registers. Either a Global Clock Buffer
(BUFG) or a BUFGMUX affords access to the global clock
network. As shown in Figure 42a, the feedback loop is cre-
ated by routing CLK0 (or CLK2X) in Figure 42b to a global
clock net, which in turn drives the CLKFB input.
In the off-chip synchronization case in Figure 42c and
Figure 42d, CLK0 (or CLK2X) plus any of the DLL’s other
output clock signals exit the FPGA using output buffers
(OBUF) to drive an external clock network plus registers on
the board. As shown in Figure 42c, the feedback loop is
formed by feeding CLK0 (or CLK2X) in Figure 42d back into
the FPGA, then to the DCM’s CLKFB input via a Global
Buffer Input, specified in Table 30.
BUFG
FPGA
CLK90
CLKIN
CLK180
CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
BUFGMUX
Clock
Net Delay
BUFGMUX
CLK0
BUFG
FPGA
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
BUFGMUX
Clock
Net Delay
CLKFB
CLK2X
BUFGMUX
CLK2X
(a) On-Chip with CLK0 Feedback
(b) On-Chip with CLK2X Feedback
FPGA
IBUFG
IBUFG
CLK90
CLK180
CLKIN CLK270
CLKDV
DCM _CLK2X
CLK2X180
CLKFB
CLK0
OBUF
OBUF
Clock
Net Delay
FPGA
IBUFG
IBUFG
CLK0
CLK90
CLKIN CLK180
CLK270
DCM CLKDV
CLK2X180
OBUF
CLKFB
CLK2X
OBUF
Clock
Net Delay
CLK0
CLK2X
(c) Off-Chip with CLK0 Feedback
(d) Off-Chip with CLK2X Feedback
DS099-2_09_082104
Figure 42: Input Clock, Output Clock, and Feedback Connections for the DLL
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
53
Product Specification