XC3S100E_06 Datasheet, PDF (231/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Pinout Descriptions
Revision History
The following table shows the revision history for this document.
Date
03/01/05
03/21/05
11/23/05
03/22/06
05/19/06
11/09/06
Version
1.0
1.1
2.0
3.0
3.1
3.4
Revision
Initial Xilinx release.
Added XC3S250E in the CP132 package to Table 128. Corrected number of differential I/O
pairs on CP132. Added pinout and footprint information for the CP132, FG400, and FG484
packages. Removed IRDY and TRDY pins from the VQ100, TQ144, and PQ208 packages.
Corrected title of Table 152. Updated differential pair numbering for some pins in Bank 0 of
the FG400 package, affecting Table 151 and Figure 88. Pin functionality and ball
assignment were not affected. Added Package Thermal Characteristics section. Added
package mass values to Table 124.
Included I/O pins, not just input-only pins under the VREF description in Table 123. Clarified
that some global clock inputs are Input-only pins in Table 123. Added information on the
XC3S100E in the CP132 package, affecting Table 128, Table 129, Table 132, Table 133,
Table 135, and Figure 82. Ball A12 on the XC3S1600E in the FG320 package a full I/O pin,
not an Input-only pin. Corrected the I/O counts for the XC3S1600E in the FG320 package,
affecting Table 128, Table 149, Table 150, and Figure 87. Corrected pin type for
XC3S1600E balls N14 and N15 in Table 147.
Minor text edits.
Added package thermal data for the XC3S100E in the CP132 package to Table 129.
Corrected pin migration arrows for balls E17 and F4 between the XC3S500E and
XC3S1600E in Table 150. Promoted Module 4 to Production status. Synchronized all
modules to v3.4.
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
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Product Specification