XC3S100E_06 Datasheet, PDF (107/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Start-Up
At the end of configuration, the FPGA automatically pulses
the Global Set/Reset (GSR) signal, placing all flip-flops in a
known state. After configuration completes, the FPGA
switches over to the user application loaded into the FPGA.
The sequence and timing of how the FPGA switches over is
programmable as is the clock source controlling the
sequence.
The default start-up sequence appears in Figure 69, where
the Global Three-State signal (GTS) is released one clock
cycle after DONE goes High. This sequence allows the
DONE signal to enable or disable any external logic used
during configuration before the user application in the FPGA
starts driving output signals. One clock cycle later, the Glo-
bal Write Enable (GWE) signal is released. This allows sig-
nals to propagate within the FPGA before any clocked
storage elements such as flip-flops and block ROM are
enabled.
The function of the dual-purpose I/O pins, such as M[2:0],
VS[2:0], HSWAP, and A[23:0], also changes when the
DONE pin goes High. When DONE is High, these pins
become user I/Os. Like all user-I/O pins, GTS controls
when the dual-purpose pins can drive out.
Start-Up Clock
Default Cycles
Phase
0 1 2 3 4 5 67
DONE
GTS
GWE
Start-Up Clock
Phase
Sync-to-DONE
0 1 2 3 4 5 67
DONE
GTS
DONE High
GWE
DS312-2_60_022305
Figure 69: Default Start-Up Sequence
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
107
Product Specification