XC3S100E_06 Datasheet, PDF (127/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
I/O Timing
Table 85: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
-0
-5
-4
Symbol
Description
Conditions
Device Abs. Min. Max
Max
Clock-to-Output Times
T_ICKOFDCM
When reading from the
Output Flip-Flop (OFF),
the time from the active
transition on the Global
Clock pin to data
appearing at the Output
pin. The DCM is iuses.
T_ICKOF
When reading from OFF,
the time from the active
transition on the Global
Clock pin to data
appearing at the Output
pin. The DCM is not used.
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, with DCM⁽³⁾
LVCMOS25⁽²⁾, 12mA
output drive, Fast slew
rate, without DCM
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
0.92
1.14
1.14
1.15
1.14
1.96
1.79
1.82
1.96
2.0
2.66
2.79
3.00
3.45
3.01
3.46
3.01
3.46
3.00
3.45
5.60
5.92
4.91
5.43
4.98
5.51
5.36
5.94
5.45
6.05
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 94 and are based on the operating conditions set forth in
Table 76 and Table 79.
2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 90. If the latter is true, add the appropriate Output adjustment from Table 93.
3. DCM output jitter is included in all measurements.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
127
Product Specification