XC3S100E_06 Datasheet, PDF (187/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Pinout Descriptions
User I/Os by Bank
Table 141 indicates how the 158 available user-I/O pins are
distributed between the four I/O banks on the PQ208 pack-
age.
Footprint Migration Differences
The XC3S250E and XC3S500E FPGAs have identical foot-
prints in the PQ208 package. Designs can migrate between
the XC3S250E and XC3S500E without further consider-
ation.
Table 141: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
38
18
6
1
5
Right
1
40
9
7
21
3
Bottom
2
40
8
6
24
2
Left
3
40
23
6
0
3
TOTAL
158
58
25
46
13
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
187
Product Specification