XC3S100E_06 Datasheet, PDF (51/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 30: Direct Clock Input Connections and Optional External Feedback to Associated DCMs
Differential Pair Differential Pair
Differential Pair Differential Pair
N
P
N
P
N
P
N
P
Package Pin Number for Single-Ended Input
Pin Number for Single-Ended Input
VQ100
P91
P90
P89
P88
P86
P85
P84
P83
CP132
B7
A7
C8
B8
A9
B9
C9
A10
TQ144
P131 P130 P129 P128
P126 P125 P123 P122
PQ208
P186 P185 P184 P183
P181 P180 P178 P177
FT256
D8
C8
B8
A8
A9
A10
F9
E9
FG320
D9
C9
B9
B8
A10
B10
E10
D10
FG400
A9
A10
G10
H10
E10
E11
G11
F11
FG484
B11
C11
H11
H12
C12
B12
E12
F12
Ð
Ð
Ð
Ð
Associated Global Buffers
Ð
Ð
Ð
Ð
GCLK11 GCLK10 GCLK9 GCLK8
GCLK7 GCLK6 GCLK5 GCLK4
Top Left DCM
XC3S100: N/A
XC3S250E, XC3S500E: DCM_X0Y1
XC3S1200E, XC3S1600E: DCM_X1Y3
Top Right DCM
XC3S100: DCM_X0Y1
XC3S250E, XC3S500E: DCM_X1Y1
XC3S1200E, XC3S1600E: DCM_X2Y3
ÐÐÐÐ
HGF E
Clock Line (see Table 41)
DCBA
ÏÏÏÏ
Bottom Left DCM
XC3S100: N/A
XC3S250E, XC3S500E: DCM_X0Y0
XC3S1200E, XC3S1600E: DCM_X1Y0
Bottom Right DCM
XC3S100: DCM_X0Y0
XC3S250E, XC3S500E: DCM_X1Y0
XC3S1200E, XC3S1600E: DCM_X2Y0
GCLK12 GCLK13 GCLK14 GCLK15
GCLK0
Ï
Ï
Ï
Ï
Associated Global Buffers
Ï
GCLK1
Ï
GCLK2
Ï
GCLK3
Ï
Differential Pair
Package P
N
Differential Pair
P
N
Differential Pair
P
N
Differential Pair
P
N
VQ100
CP132
TQ144
PQ208
FT256
FG320
FG400
FG484
Pin Number for Single-Ended Input
P32
P33
P35
P36
M4
N4
M5
N5
P50
P51
P53
P54
P74
P75
P77
P78
M8
L8
N8
P8
N9
M9
U9
V9
W9
W10
R10
P10
V11
U11
R11
T11
Pin Number for Single-Ended Input
P38
P39
P40
P41
M6
N6
P6
P7
P56
P57
P58
P59
P80
P81
P82
P83
T9
R9
P9
N9
U10
T10
R10
P10
P11
P12
V10
V11
R12
P12
Y12
W12
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
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Product Specification