XC3S100E_06 Datasheet, PDF (60/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
BUFGMUX
pair
BUFGMUX
H
G
2
2
DCM
XC3S1200E (X0Y1)
XC3S1600E (X0Y1)
2
2
F
Global Clock Inputs
4 ^{GCLK11 GCLK10 GCLK9 GCLK8}
GCLK7 GCLK6 GCLK5 GCLK4 ₄
DCM
XC3S250E (X0Y1)
XC3S500E (X0Y1)
XC3S1200E (X1Y3) 4
XC3S1600E (X1Y3)
Top Left
Quadrant (TL)
8
•
X1Y10 X1Y11 X2Y10 X2Y11
HG
FE
4
DCM
XC3S100E (X0Y1)
XC3S250E (X1Y1)
4
XC3S500E (X1Y1)
XC3S1200E (X2Y3)
XC3S1600E (X2Y3)
Top Right
8
Quadrant (TR)
•
8
8
•
8
•
8
•
•
Clock Line
in Quadrant
H
G
2
2
DCM
XC3S1200E (X3Y1)
XC3S1600E (X3Y1)
2
2
F
E
D
C
2
2
DCM
XC3S1200E (X0Y2)
XC3S1600E (X0Y2)
2
2
B
Left Spine 8 ^{Note 3} 8
Note 3
•
8
8
•
•
Horizontal Spine
8
Note 4 _{8 Right Spine}
E
Note 4
D
•
C
8
2
2
•
8
DCM
XC3S1200E (X3Y2)
XC3S1600E (X3Y2)
2
•
2
B
Bottom Left
8
4
A Quadrant (BL)
8
Bottom Right
Quadrant (BR) _A
DCM
4
XC3S250E (X0Y0)
XC3S500E (X0Y0)
XC3S1200E (X1Y0)
XC3S1600E (X1Y0)
DC
X1Y0 X1Y1
BA
X2Y0 X2Y1
4
4
DCM
XC3S100E (X0Y0)
XC3S250E (X1Y0)
XC3S500E (X1Y0)
XC3S1200E (X2Y0)
XC3S1600E (X2Y0)
4 ^{GCLK3 GCLK2 GCLK1 GCLK0}
GCLK15 GCLK14 GCLK13 GCLK12
Global Clock Inputs
DS312-2_04_041106
Notes:
1. The diagram presents electrical connectivity. The diagram locations do not necessarily match the physical location on the device,
although the coordinate locations shown are correct.
2. Number of DCMs and locations of these DCM varies for different device densities. The left and right DCMs are only in the
XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die.
3. See Figure 47a, which shows how the eight clock lines are multiplexed on the left-hand side of the device.
4. See Figure 47b, which shows how the eight clock lines are multiplexed on the right-hand side of the device.
5. For best direct clock inputs to a particular clock buffer, not a DCM, see Table 41.
6. For best direct clock inputs to a particular DCM, not a BUFGMUX, see Table 30, Table 31, and Table 32. Direct pin inputs to a DCM
are shown in gray.
Figure 45: Spartan-3E Internal Quadrant-Based Clock Network (Electrical Connectivity View)
60
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DS312-2 (v3.4) November 9, 2006
Product Specification