XC3S100E_06 Datasheet, PDF (55/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
The CLKFX_DIVIDE is an integer ranging from 1 to 32,
inclusive and forms the denominator in Equation 1. For
example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3,
the frequency of the output clock signal is 5/3 that of the
input clock signal. These attributes and their acceptable
ranges are described in Table 34.
Table 34: DFS Attributes
Attribute
Description
Values
CLKFX_MULTIPLY
Frequency
multiplier
constant
Integer from
2 to 32,
inclusive
CLKFX_DIVIDE
Frequency divisor Integer from
constant
1 to 32,
inclusive
Any combination of integer values can be assigned to the
CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, pro-
vided that two conditions are met:
1. The two values fall within their corresponding ranges,
as specified in Table 34.
2. The f_CLKFX output frequency calculated in Equation 1
falls within the DCM’s operating frequency
specifications (see Table 106 in Module 3).
DFS With or Without the DLL
Although the CLKIN input is shared with both units, the DFS
unit functions with or separately from the DLL unit. Separate
from the DLL, the DFS generates an output frequency from
the CLKIN frequency according to the respective
CLKFX_MULTIPLY and CLKFX_DIVIDE values. Frequency
synthesis does not require a feedback loop. Furthermore,
without the DLL, the DFS unit supports a broader operating
frequency range.
With the DLL, the DFS unit operates as described above,
only with the additional benefit of eliminating the clock distri-
bution delay. In this case, a feedback loop from the CLK0 or
CLK2X output to the CLKFB input must be present.
When operating with the DLL unit, the DFS’s CLKFX and
CLKFX180 outputs are phase-aligned with the CLKIN input
every CLKFX_DIVIDE cycles of CLKIN and every
CLKFX_MULTIPLY cycles of CLKFX. For example, when
CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE = 3, the input
and output clock edges coincide every three CLKIN input
periods, which is equivalent in time to five CLKFX output
periods.
Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values
result in faster lock times. Therefore, CLKFX_MULTIPLY
and CLKFX_DIVIDE must be factored to reduce their values
wherever possible. For example, given CLKFX_MULTIPLY
= 9 and CLKFX_DIVIDE = 6, removing a factor of three
yields CLKFX_MULTIPLY = 3 and CLKFX_DIVIDE = 2.
While both value-pairs result in the multiplication of clock
frequency by 3/2, the latter value-pair enables the DLL to
lock more quickly.
Phase Shifter (PS)
The DCM provides two approaches to controlling the phase
of a DCM clock output signal relative to the CLKIN signal:
First, eight of the nine DCM clock outputs – CLK0, CLK90,
CLK180, CLK270, CLK2X, CLK2X180, CLKFX, and
CLKFX180 – provide either quadrant or half-period phase
shifting of the input clock.
Second, the PS unit provides additional fine phase shift
control of all nine DCM outputs. The PS unit accomplishes
this by introducing a “fine phase shift” delay (T_PS) between
the CLKFB and CLKIN signals inside the DLL unit. In FIXED
phase shift mode, the fine phase shift is specified at design
time with a resolution down to ¹/_256th of a CLKIN cycle or
one delay step (DCM_DELAY_STEP), whichever is greater.
This fine phase shift value is relative to the coarser quadrant
or half-period phase shift of the DCM clock output. When
used, the PS unit shifts the phase of all nine DCM clock out-
put signals.
Enabling Phase Shifting and Selecting an Operat-
ing Mode
The CLKOUT_PHASE_SHIFT attribute controls the PS unit
for the specific DCM instantiation. As described in Table 35,
this attribute has three possible values: NONE, FIXED, and
VARIABLE. When CLKOUT_PHASE_SHIFT = NONE, the
PS unit is disabled and the DCM output clocks are
phase-aligned to the CLKIN input via the CLKFB feedback
path. Figure 44a shows this case.
The PS unit is enabled when the CLKOUT_PHASE_SHIFT
attribute is set to FIXED or VARIABLE modes. These two
modes are described in the sections that follow.
Table 35: PS Attributes
Attribute
CLKOUT_PHASE_SHIFT
PHASE_SHIFT
Description
Disables the PS component or chooses between
Fixed Phase and Variable Phase modes.
Determines size and direction of initial fine phase
shift.
Values
NONE, FIXED, VARIABLE
Integers from –255 to +255
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
55
Product Specification