XC3S100E_06 Datasheet, PDF (80/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Table 54: Serial Peripheral Interface (SPI) Connections
FPGA
Pin Name Direction
Description
During Configuration
After Configuration
HSWAP
P
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank V_CCO input.
0: Pull-ups during configuration
1: No pull-ups
Drive at valid logic level
throughout configuration.
User I/O
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
User I/O
VS[2:0]
S
Input
Variant Select. Instructs the FPGA how
to communicate with the attached SPI
Flash PROM. See Design
Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins.
Must be at the logic levels
shown in Table 52. Sampled
when INIT_B goes High.
User I/O
MOSI
Output Serial Data Output.
FPGA sends SPI Flash memory
read commands and starting
address to the PROM’s serial
data input.
User I/O
DIN
Input
Serial Data Input.
FPGA receives serial data from User I/O
PROM’s serial data output.
CSO_B
Output Chip Select Output. Active Low.
Connects to the SPI Flash
PROM’s chip-select input. If
HSWAP = 1, connect this signal
to a 4.7 kΩ pull-up resistor to
3.3V.
Drive CSO_B High after
configuration to disable the
SPI Flash and reclaim the
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
CCLK
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity. See CCLK Design
Considerations.
Drives PROM’s clock input.
User I/O
DOUT
Output Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
User I/O
80
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DS312-2 (v3.4) November 9, 2006
Product Specification