XC3S100E_06 Datasheet, PDF (128/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 86: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
Symbol
Description
IFD_
-5
-4
DELAY_
Conditions
VALUE=
Device
Min
Min
Setup Times
T_PSDCM
When writing to the Input
LVCMOS25⁽²⁾,
0 XC3S100E
2.65
2.98
Flip-Flop (IFF), the time from the IFD_DELAY_VALUE = 0,
setup of data at the Input pin to with DCM⁽⁴⁾
XC3S250E
2.25
2.59
the active transition at a Global
XC3S500E
2.25
2.59
Clock pin. The DCM is used. No
XC3S1200E
2.25
2.58
Input Delay is programmed.
XC3S1600E
2.25
2.59
T_PSFD
When writing to IFF, the time
LVCMOS25⁽²⁾,
2 XC3S100E
2.24
2.31
from the setup of data at the
IFD_DELAY_VALUE =
Input pin to an active transition default software setting
3 XC3S250E
3.19
3.33
at the Global Clock pin. The
3 XC3S500E
3.91
4.61
DCM is not used. The Input
Delay is programmed.
3 XC3S1200E
2.57
3.28
3 XC3S1600E
3.20
3.56
Hold Times
T_PHDCM
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is used. No
Input Delay is programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE = 0,
with DCM⁽⁴⁾
T_PHFD
When writing to IFF, the time
from the active transition at the
Global Clock pin to the point
when data must be held at the
Input pin. The DCM is not used.
The Input Delay is programmed.
LVCMOS25⁽³⁾,
IFD_DELAY_VALUE =
default software setting
0 XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
2 XC3S100E
3 XC3S250E
3 XC3S500E
3 XC3S1200E
3 XC3S1600E
–0.54
0.06
0.07
0.07
0.06
0.00
–0.50
–0.77
0.32
–0.15
–0.52
0.14
0.14
0.15
0.14
0.07
–0.49
–0.75
0.37
–0.11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 94 and are based on the operating conditions set forth in
Table 76 and Table 79.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 90. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 90. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4. DCM output jitter is included in all measurements.
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DS312-3 (v3.4) November 9, 2006
Product Specification