XC3S100E_06 Datasheet, PDF (61/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following
sources: two GCLK pins, two DCM outputs, or one Dou-
ble-Line interconnect.
Table 41 indicates permissible connections between clock
inputs and BUFGMUX elements. The I0-input provides the
best input path to a clock buffer. The I1-input provides the
secondary input for the clock multiplexer function.
The four BUFGMUX elements on the top edge are paired
together and share inputs from the eight global clock inputs
along the top edge. Each BUFGMUX pair connects to four
of the eight global clock inputs, as shown in Figure 45. This
optionally allows differential inputs to the global clock inputs
without wasting a BUFGMUX element.
Table 41: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadrant
Left-Half BUFGMUX
Top or Bottom BUFGMUX
Clock
Line⁽¹⁾ Location⁽²⁾ I0 Input I1 Input Location⁽²⁾ I0 Input
I1 Input
Right-Half BUFGMUX
Location⁽²⁾ I0 Input I1 Input
H
X0Y9
LHCLK7 LHCLK6
X1Y10
GCLK7 or GCLK6 or
GCLK11 GCLK10
X3Y9
RHCLK3 RHCLK2
G
X0Y8
LHCLK6 LHCLK7
X1Y11
GCLK6 or GCLK7 or
GCLK10 GCLK11
X3Y8
RHCLK2 RHCLK3
F
X0Y7
LHCLK5 LHCLK4
X2Y10
GCLK5 or GCLK4 or
GCLK9 GCLK8
X3Y7
RHCLK1 RHCLK0
E
X0Y6
LHCLK4 LHCLK5
X2Y11
GCLK4 or GCLK5 or
GCLK8 GCLK9
X3Y6
RHCLK0 RHCLK1
D
X0Y5
LHCLK3 LHCLK2
X1Y0
GCLK3 or GCLK2 or
GCLK15 GCLK14
X3Y5
RHCLK7 RHCLK6
C
X0Y4
LHCLK2 LHCLK3
X1Y1
GCLK2 or GCLK3 or
GCLK14 GCLK15
X3Y4
RHCLK6 RHCLK7
B
X0Y3
LHCLK1 LHCLK0
X2Y0
GCLK1 or GCLK0 or
GCLK13 GCLK12
X3Y3
RHCLK5 RHCLK4
A
X0Y2
LHCLK0 LHCLK1
X2Y1
GCLK0 or GCLK1 or
GCLK12 GCLK13
X3Y2
RHCLK4 RHCLK5
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 45 for specific BUFGMUX locations, and Figure 47 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
The connections for the bottom-edge BUFGMUX elements On the left and right edges, only two clock inputs feed each
are similar to the top-edge connections (see Figure 46).
pair of BUFGMUX elements.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
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Product Specification