XC3S100E_06 Datasheet, PDF (141/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 101: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Combinatorial Delay
T_MULT
Combinatorial multiplier propagation delay from the A and B
inputs to the P outputs, assuming 18-bit inputs and a 36-bit
product (AREG, BREG, and PREG registers unused)
Clock-to-Output Times
T_{MSCKP_P}
Clock-to-output delay from the active transition of the CLK
input to valid data appearing on the P outputs when using
the PREG register⁽²⁾
T_{MSCKP_A}
T_{MSCKP_B}
Clock-to-output delay from the active transition of the CLK
input to valid data appearing on the P outputs when using
either the AREG or BREG register^(2,4)
Setup Times
T_{MSDCK_P}
Data setup time at the A or B input before the active
transition at the CLK when using only the PREG output
register (AREG, BREG registers unused)
T_{MSDCK_A}
Data setup time at the A input before the active transition at
the CLK when using the AREG input register⁽⁴⁾
T_{MSDCK_B}
Data setup time at the B input before the active transition at
the CLK when using the BREG input register⁽⁴⁾
Hold Times
T_MULCKID
Data hold time at the A and B inputs after the active
transition at the CLK input
Clock Frequency
F_MULT
Internal operating frequency for a two-stage 18x18
multiplier using the AREG and BREG input registers and
the PREG output register⁽¹⁾
Speed Grade
-5
-4
Min Max Min Max
Units
-
4.34⁽¹⁾
-
4.88⁽¹⁾ ns
-
0.98
-
1.10 ns
-
4.42
-
4.97 ns
3.54
-
3.98
-
ns
0.20
-
0.23
-
ns
0.35
-
0.39
-
ns
0
-
0
-
ns
0
270
0
240 MHz
Notes:
1. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. The PREG register is typically used when inferring a single-stage multiplier.
4. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
141
Product Specification