XC3S100E_06 Datasheet, PDF (112/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
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Although the FPGA has no specific voltage sequence
requirements, be sure to consider any potential sequencing
requirement of the configuration device attached to the
FPGA, such as an SPI serial Flash PROM, a parallel NOR
Flash PROM, or a microcontroller. For example, Flash
PROMs have a minimum time requirement before the
PROM can be selected and this must be considered if the
3.3V supply is the last in the sequence. See Power-On Pre-
cautions if 3.3V Supply is Last in Sequence for more
details.
When all three supplies are valid, the minimum current
required to power-on the FPGA equals the worst-case qui-
escent current, specified in Table 78. Spartan-3E FPGAs do
not require Power-On Surge (POS) current to successfully
configure.
Surplus I_CCINT if V_CCINT Applied before V_CCAUX
If the V_CCINT supply is applied before the V_CCAUX supply,
the FPGA might draw a surplus I_CCINT current in addition to
the I_CCINT quiescent current levels specified in Table 78,
page 121. The momentary additional I_CCINT surplus current
might be a few hundred milliamperes under nominal condi-
tions, significantly less than the instantaneous current con-
sumed by the bypass capacitors at power-on. However, the
surplus current immediately disappears when the V_CCAUX
supply is applied, and, in response, the FPGA’s I_CCINT qui-
escent current demand drops to the levels specified in
Table 78. The FPGA does not use or require the surplus
current to successfully power-on and configure. If applying
V_CCINT before V_CCAUX, ensure that the regulator does not
have a foldback feature that could inadvertently shut down
in the presence of the surplus current.
Configuration Data Retention, Brown-Out
The FPGA’s configuration data is stored in robust CMOS
configuration latches. The data in these latches is retained
even when the voltages drop to the minimum levels neces-
sary to preserve RAM contents, as specified in Table 75.
If, after configuration, the V_CCAUX or V_CCINT supply drops
below its data retention voltage, the current device configu-
ration must be cleared using one of the following methods:
• Force the V_CCAUX or V_CCINT supply voltage below the
minimum Power On Reset (POR) voltage threshold
(Table 73).
• Assert PROG_B Low.
The POR circuit does not monitor the VCCO_2 supply after
configuration. Consequently, dropping the VCCO_2 voltage
does not reset the device by triggering a Power-On Reset
(POR) event.
No Internal Charge Pumps or Free-Running
Oscillators
Some system applications are sensitive to sources of ana-
log noise. Spartan-3E FPGA circuitry is fully static and does
not employ internal charge pumps.
The CCLK configuration clock is active during the FPGA
configuration process. After configuration completes, the
CCLK oscillator is automatically disabled unless the Bit-
stream Generator (BitGen) option Persist=Yes.
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DS312-2 (v3.4) November 9, 2006
Product Specification