XC3S100E_06 Datasheet, PDF (121/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Quiescent Current Requirements
Table 78: Quiescent Supply Current Characteristics
Symbol
Description
Device
I_CCINTQ Quiescent V_CCINT supply current XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
I_CCOQ
Quiescent V_CCO supply current
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
I_CCAUXQ Quiescent V_CCAUX supply
current
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Typical⁽²⁾
8
15
25
50
65
1.5
1.5
2
3
3
8
12
18
35
45
Commercial
Maximum⁽²⁾
60
120
165
400
560
8
8
10
12
12
25
30
40
65
80
Industrial
Maximum⁽²⁾
80
160
210
500
700
10
10
12
15
15
28
35
45
75
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. The numbers in this table are based on the conditions set forth in Table 76.
2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at ambient room temperature (T_A of 25°C at V_CCINT = 1.2 V, V_CCO = 3.3V,
and V_CCAUX = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at
maximum voltage limits with V_CCINT = 1.26V, V_CCO = 3.45V, and V_CCAUX = 2.625V. The FPGA is programmed with a “blank” configuration
data file (i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including
functional elements), measured quiescent current levels may be different than the values in the table.
3. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3E XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower
Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates.
4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
121
Product Specification