XC3S100E_06 Datasheet, PDF (173/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Table 132: CP132 Package Pinout (Continued)
Bank
XC3S100E
Pin Name
XC3S250E
XC3S500E
Pin Name
2
IO_L06P_2/D2/GCLK2
IO_L06P_2/D2/GCLK2
2
IO_L07N_2/DIN/D0
IO_L07N_2/DIN/D0
2
IO_L07P_2/M0
2
N.C. (‹)
IO_L07P_2/M0
IO_L08N_2/A22
2
N.C. (‹)
IO_L08P_2/A23
2
N.C. (‹)
IO_L09N_2/A20
2
N.C. (‹)
IO_L09P_2/A21
2
IO_L10N_2/VS1/A18
2
IO_L10P_2/VS2/A19
2
IO_L11N_2/CCLK
2
IO_L11P_2/VS0/A17
2
IP/VREF_2
2
IP_L05N_2/M2/GCLK1
2
IP_L05P_2/RDWR_B/GCLK0
2
VCCO_2
2
VCCO_2
3
IO
3
IP/VREF_3
IO_L10N_2/VS1/A18
IO_L10P_2/VS2/A19
IO_L11N_2/CCLK
IO_L11P_2/VS0/A17
IP/VREF_2
IP_L05N_2/M2/GCLK1
IP_L05P_2/RDWR_B/GCLK0
VCCO_2
VCCO_2
IO
IO/VREF_3
3
IO_L01N_3
3
IO_L01P_3
3
IO_L02N_3
3
IO_L02P_3
3
N.C. (‹)
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
3
IO
3
IO_L04N_3/LHCLK1
3
IO_L04P_3/LHCLK0
3
IO_L05N_3/LHCLK3/IRDY2
3
IO_L05P_3/LHCLK2
3
IO_L06N_3/LHCLK5
3
IO_L06P_3/LHCLK4/TRDY2
3
IO_L07N_3/LHCLK7
3
IO_L07P_3/LHCLK6
3
IO_L08N_3
3
IO_L08P_3
3
IO_L09N_3
IO_L03P_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
IO_L08P_3
IO_L09N_3
DS312-4 (v3.4) November 9, 2006
Product Specification
www.xilinx.com
Pinout Descriptions
CP132 Ball
P6
N8
P8
M9
N9
M10
N10
M11
N11
N12
P12
N3
N6
M6
M8
P3
J3
K3
B1
B2
C2
C3
D1
D2
F2
F3
G1
F1
H1
G3
H3
H2
L2
L1
M1
Type
DUAL/GCLK
DUAL
DUAL
100E: N.C.
Others: DUAL
100E: N.C.
Others: DUAL
100E: N.C.
Others: DUAL
100E: N.C.
Others: DUAL
DUAL
DUAL
DUAL
DUAL
VREF
DUAL/GCLK
DUAL/GCLK
VCCO
VCCO
I/O
100E: VREF(INPUT)
Others: VREF(I/O)
I/O
I/O
I/O
I/O
100E: N.C.
Others: I/O
I/O
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
I/O
I/O
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