XC3S100E_06 Datasheet, PDF (17/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
Differential pairs can be shown in the Pin and Area Con-
straints Editor (PACE) with the “Show Differential Pairs”
option. A unique L-number, part of the pin name, identifies
the line-pairs associated with each bank (see Pinout
Descriptions in Module 4). For each pair, the letters P and
N designate the true and inverted lines, respectively. For
example, the pin names IO_L43P_3 and IO_L43N_3 indi-
cate the true and inverted lines comprising the line pair L43
on Bank 3.
V_CCO provides current to the outputs and additionally pow-
ers the On-Chip Differential Termination. V_CCO must be
2.5V when using the On-Chip Differential Termination. The
V_REF lines are not required for differential operation.
To further understand how to combine multiple IOSTAN-
DARDs within a bank, refer to IOBs Organized into Banks,
page 18.
On-Chip Differential Termination
Spartan-3E devices provide an on-chip ~120Ω differential
termination across the input differential receiver terminals.
The on-chip input differential termination in Spartan-3E
devices potentially eliminates the external 100Ω termination
resistor commonly found in differential receiver circuits. Dif-
ferential termination is used for LVDS, mini-LVDS, and
RSDS as applications permit.
On-chip Differential Termination is available in banks with
V_CCO = 2.5V and is not supported on dedicated input pins.
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = “<TRUE/FALSE>”;
Spartan-3E
Differential
Output
Z0 = 50Ω
Spartan-3E
Differential Input
Spartan-3E
Differential
Output
Z0 = 50Ω
Z0 = 50Ω
Spartan-3E
Differential Input
with On-Chip
Differential
Terminator
Z0 = 50Ω
DS312-2_24_082605
Figure 11: Differential Inputs and Outputs
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O or Input-only pin to a determined state.
Pull-up and pull-down resistors are commonly applied to
unused I/Os, inputs, and three-state outputs, but can be
used on any I/O or Input-only pin. The pull-up resistor con-
nects an IOB to V_CCO through a resistor. The resistance
value depends on the V_CCO voltage (see DC and Switch-
ing Characteristics in Module 3 for the specifications). The
pull-down resistor similarly connects an IOB to ground with
a resistor. The PULLUP and PULLDOWN attributes and
library primitives turn on these optional resistors.
By default, PULLDOWN resistors terminate all unused I/O
and Input-only pins. Unused I/O and Input-only pins can
alternatively be set to PULLUP or FLOAT. To change the
unused I/O Pad setting, set the Bitstream Generator (Bit-
Gen) option UnusedPin to PULLUP, PULLDOWN, or
FLOAT. The UnusedPin option is accessed through the
Properties for Generate Programming File in ISE. See Bit-
stream Generator (BitGen) Options.
During configuration a Low logic level on the HSWAP pin
activates pull-up resistors on all I/O and Input-only pins not
actively used in the selected configuration mode.
Keeper Circuit
Each I/O has an optional keeper circuit (see Figure 12) that
keeps bus lines from floating when not being actively driven.
The KEEPER circuit retains the last logic level on a line after
all drivers have been turned off. Apply the KEEPER
attribute or use the KEEPER library primitive to use the
KEEPER circuitry. Pull-up and pull-down resistors override
the KEEPER settings.
Weak Pull-up
Output Path
Input Path
Keeper
Weak Pull-down
DS312-2_25_022805
Figure 12: Keeper Circuit
Slew Rate Control and Drive Strength
Each IOB has a slew-rate control that sets the output
switching edge-rate for LVCMOS and LVTTL outputs. The
SLEW attribute controls the slew rate and can either be set
to SLOW (default) or FAST.
Each LVCMOS and LVTTL output additionally supports up
to six different drive current strengths as shown in Table 8.
To adjust the drive strength for each output, the DRIVE
attribute is set to the desired drive strength: 2, 4, 6, 8, 12,
and 16. Unless otherwise specified in the FPGA application,
the software default IOSTANDARD is LVCMOS25, SLOW
slew rate, and 12 mA output drive.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
17
Product Specification