XC3S100E_06 Datasheet, PDF (83/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
ConfigRate = 12 or lower. SPI Flash PROMs that support
the FAST READ command support higher data rates. Some
such PROMs support up to ConfigRate = 25 and beyond
but require careful data sheet analysis. See Serial Periph-
eral Interface (SPI) Configuration Timing for more
detailed timing analysis.
Using the SPI Flash Interface after Configuration
After the FPGA successfully completes configuration, all of
the pins connected to the SPI Flash PROM are available as
user-I/O pins.
If not using the SPI Flash PROM after configuration, drive
CSO_B High to disable the PROM. The MOSI, DIN, and
CCLK pins are then available to the FPGA application.
Because all the interface pins are user I/O after configura-
tion, the FPGA application can continue to use the SPI
Flash interface pins to communicate with the SPI Flash
PROM, as shown in Figure 56. SPI Flash PROMs offer ran-
dom-accessible, byte-addressable, read/write, non-volatile
storage to the FPGA application.
SPI Flash PROMs are available in densities ranging from
1 Mbit up to 128 Mbits. However, a single Spartan-3E
FPGA requires less than 6 Mbits. If desired, use a larger
SPI Flash PROM to contain additional non-volatile applica-
tion data, such as MicroBlaze processor code, or other user
data such as serial numbers and Ethernet MAC IDs. In the
example shown in Figure 56, the FPGA configures from SPI
Flash PROM. Then using FPGA logic after configuration,
the FPGA copies MicroBlaze code from SPI Flash into
external DDR SDRAM for code execution. Similarly, the
FPGA application can store non-volatile application data
within the SPI Flash PROM.
The FPGA configuration data is stored starting at location 0.
Store any additional data beginning in the next available
SPI Flash PROM sector or page. Do not mix configuration
data and user data in the same sector or page.
Similarly, the SPI bus can be expanded to additional SPI
peripherals. Because SPI is a common industry-standard
interface, various SPI-based peripherals are available, such
as analog-to-digital (A/D) converters, digital-to-analog (D/A)
converters, CAN controllers, and temperature sensors.
However, if sufficient I/O pins are available in the applica-
tion, Xilinx recommends creating a separate SPI bus to con-
trol peripherals. Creating a second port reduces the loading
on the CCLK and DIN pins, which are crucial for configura-
tion.
The MOSI, DIN, and CCLK pins are common to all SPI
peripherals. Connect the select input on each additional SPI
peripheral to one of the FPGA user I/O pins. If HSWAP = 0
during configuration, the FPGA holds the select line High. If
HSWAP = 1, connect the select line to +3.3V via an external
4.7 kΩ pull-up resistor to avoid spurious read or write oper-
ations. After configuration, drive the select line Low to select
the desired SPI peripheral.
During the configuration process, CCLK is controlled by the
FPGA and limited to the frequencies generated by the
FPGA. After configuration, the FPGA application can use
other clock signals to drive the CCLK pin and can further
optimize SPI-based communication.
Refer to the individual SPI peripheral data sheet for specific
interface and communication protocol requirements.
Spartan-3E FPGA
FPGA-based
SPI Master
MOSI
DIN
CCLK
CSO_B
User I/O
+3.3V
SPI Serial Flash PROM
DATA_IN
DATA_OUT
CLOCK
SELECT
User Data
MicroBlaze
Code
FPGA
Configuration
FFFFF
0
SPI Peripherals
DATA_IN
DATA_OUT
CLOCK
SELECT
- A/D Converter
- D/A Converter
- CAN Controller
- Displays
- Temperature Sensor
- ASSP
To other SPI slave peripherals
Figure 56: Using the SPI Flash Interface After Configuration
DS312-2_47_022806
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
83
Product Specification