XC3S100E_06 Datasheet, PDF (58/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
The eight bits of the STATUS bus are described in Table 38.
Table 37: Status Logic Signals
Signal
Direction
RST
Input
STATUS[7:0]
Output
LOCKED
Output
Description
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for
a delay of zero. Sets the LOCKED output Low. This input is asynchronous.
The bit values on the STATUS bus provide information regarding the state of DLL and
PS operation
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two
signals are out-of-phase when Low.
Table 38: DCM Status Bus
Bit
Name
Description
0 Reserved
-
1 CLKIN Stopped When High, indicates that the CLKIN input signal is not toggling. When Low, indicates CLKIN
is toggling. This bit functions only when the CLKFB input is connected.⁽¹⁾
2 CLKFX Stopped When High, indicates that the CLKFX output is not toggling. When Low, indicates the CLKFX
output is toggling. This bit functions only when the CLKFX or CLKFX180 output are connected.
3-6 Reserved
-
Notes:
1. When only the DFS clock outputs but none of the DLL clock outputs are used, this bit does not go High when the CLKIN signal stops.
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DS312-2 (v3.4) November 9, 2006
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