XC3S100E_06 Datasheet, PDF (95/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
+1.2V
V
Intelligent
Download Host
Configuration
Memory
Source
- Internal memory
- Disk drive
- Over network
- Over RF link
VCC
D[7:0]
BUSY
SELECT
READ/WRITE
CLOCK
PROG_B
DONE
INIT_B
GND
- Microcontroller
- Processor
- Tester
- Computer
VCCINT
P
HSWAP
VCCO_0
Slave
Parallel
Mode
‘1’
‘1’
‘0’
VCCO_2
M2
M1
M0
Spartan-3E
D[7:0] _FPGA
BUSY
CSI_B
CSO_B
RDWR_B
INIT_B
CCLK
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
V
V
+2.5V
+2.5V
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
Figure 61: Slave Parallel Configuration Mode
DS312-2_52_103105
Slave Parallel Mode
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host,
such as a microprocessor or microcontroller, writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in Figure 61.
The external download host starts the configuration process
by pulsing PROG_B and monitoring that the INIT_B pin
goes High, indicating that the FPGA is ready to receive its
first data. The host asserts the active-Low chip-select signal
(CSI_B) and the active-Low Write signal (RDWR_B). The
host then continues supplying data and clock signals until
either the FPGA’s DONE pin goes High, indicating a suc-
cessful configuration, or until the FPGA’s INIT_B pin goes
Low, indicating a configuration error.
The FPGA captures data on the rising CCLK edge. If the
CCLK frequency exceeds 50 MHz, then the host must also
monitor the FPGA’s BUSY output. If the FPGA asserts
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency
is 50 MHz or below, the BUSY pin may be ignored but
actively drives during configuration.
The configuration process requires more clock cycles than
indicated from the configuration file size. Additional clocks
are required during the FPGA’s start-up sequence, espe-
cially if the FPGA is programmed to wait for selected Digital
Clock Managers (DCMs) to lock to their respective clock
inputs (see Start-Up, page 107).
If the Slave Parallel interface is only used to configure the
FPGA, never to read data back, then the RDWR_B signal
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
95
Product Specification