XC3S100E_06 Datasheet, PDF (164/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Pinout Descriptions
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Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table 126.
Table 126: Xilinx Package Mechanical Drawings
Package
Web Link (URL)
VQ100 / VQG100
http://www.xilinx.com/bvdocs/packages/vq100.pdf
CP132 / CPG132
http://www.xilinx.com/bvdocs/packages/cp132.pdf
TQ144 / TQG144
http://www.xilinx.com/bvdocs/packages/tq144.pdf
PQ208 / PQG208
http://www.xilinx.com/bvdocs/packages/pq208.pdf
FT256 / FTG256
http://www.xilinx.com/bvdocs/packages/ft256.pdf
FG320 / FGG320
http://www.xilinx.com/bvdocs/packages/fg320.pdf
FG400 / FGG400
http://www.xilinx.com/bvdocs/packages/fg400.pdf
FG484 / FGG484
http://www.xilinx.com/bvdocs/packages/fg484.pdf
Package Pins by Type
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions vary by package, as shown in Table 127.
Table 127: Power and Ground Supply Pins by Package
Package VCCINT VCCAUX VCCO GND
VQ100
4
4
8
12
CP132
6
4
8
16
TQ144
4
4
9
13
PQ208
4
8
12
20
FT256
8
8
16
28
FG320
8
8
20
28
FG400
16
8
24
42
FG484
16
10
28
48
A majority of package pins are user-defined I/O or input
pins. However, the numbers and characteristics of these I/O
depend on the device type and the package in which it is
available, as shown in Table 128. The table shows the max-
imum number of single-ended I/O pins available, assuming
that all I/O-, INPUT-, DUAL-, VREF-, and CLK-type pins are
used as general-purpose I/O. Likewise, the table shows the
maximum number of differential pin-pairs available on the
package. Finally, the table shows how the total maximum
user-I/Os are distributed by pin type, including the number
of unconnected—i.e., N.C.—pins on the device.
164
www.xilinx.com
DS312-4 (v3.4) November 9, 2006
Product Specification