XC3S100E_06 Datasheet, PDF (170/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Pinout Descriptions
VQ100 Footprint
In Figure 81, note pin 1 indicator in top-left corner and logo
orientation.
PROG_B 1
IO_L01P_3 2
IO_L01N_3 3
IO_L02P_3 4
IO_L02N_3/VREF_3 5
VCCINT 6
GND 7
VCCO_3 8
IO_L03P_3/LHCLK0 9
IO_L03N_3/LHCLK1 10
IO_L04P_3/LHCLK2 11
IO_L04N_3/LHCLK3 12
IP 13
GND 14
IO_L05P_3/LHCLK4 15
IO_L05N_3/LHCLK5 16
IO_L06P_3/LHCLK6 17
IO_L06N_3/LHCLK7 18
GND 19
VCCO_3 20
VCCAUX 21
IO_L07P_3 22
IO_L07N_3 23
IO_L01P_2/CSO_B 24
IO_L01N_2/INIT_B 25
Bank 0
Bank 2
R
75 TMS
74 VCCAUX
73 VCCO_1
72 GND
71 IO_L07N_1
70 IO_L07P_1
69 IP/VREF_1
68 IO_L06N_1/RHCLK7
67 IO_L06P_1/RHCLK6
66 IO_L05N_1/RHCLK5
65 IO_L05P_1/RHCLK4
64 GND
63 IO_L04N_1/RHCLK3
62 IO_L04P_1/RHCLK2
61 IO_L03N_1/RHCLK1
60 IO_L03P_1/RHCLK0
59 GND
58 IO_L02N_1
57 IO_L02P_1
56 VCCINT
55 VCCO_1
54 IO_L01N_1
53 IO_L01P_1
52 GND
51 DONE
Figure 81: VQ100 Package Footprint (top view).
DS312-4_02_030705
16
I/O: Unrestricted,
general-purpose user I/O
1
INPUT: Unrestricted,
general-purpose input pin
2
CONFIG: Dedicated
configuration pins
0 ^{N.C.: Not connected}
21
DUAL: Configuration pin, then
possible user-I/O
4
VREF: User I/O or input
voltage reference for bank
24
CLK: User I/O, input, or global
buffer input
8
VCCO: Output voltage supply
for bank
4
JTAG: Dedicated JTAG port
pins
4
VCCINT: Internal core supply
voltage (+1.2V)
12 ^{GND: Ground}
4
VCCAUX: Auxiliary supply
voltage (+2.5V)
170
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DS312-4 (v3.4) November 9, 2006
Product Specification