XC3S100E_06 Datasheet, PDF (105/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
Power-O n
Set PROG_B Low
after Power-On
V_CCINT >1V
and V_CCAUX > 2V
No
and V_CCO Bank 2 > 1V
Yes
Clear configuration
memory
Yes _{PROG_B = Low}
No
No
INIT_ B = High?
Yes
M[2:0] and VS[2:0]
Sample mode pins _{pins are sampled on}
INIT_B rising edge
Load configuration
data frames
CRC
No
correct?
INIT_B goes Low.
Abort Start-Up
Yes
Start-Up
sequence
DONE pin goes High,
signaling end of
configuration
User mode
No
Yes
Reconfigure?
DS312-2_58_051706
Figure 67: General Configuration Process
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
105
Product Specification