XC3S100E_06 Datasheet, PDF (115/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
Revision History
The following table shows the revision history for this document.
Date
03/01/05
03/21/05
11/23/05
03/22/06
04/10/06
05/19/06
05/30/06
Version
1.0
1.1
2.0
3.0
3.1
3.2
3.2.1
Revision
Initial Xilinx release.
Updated Figure 45. Modified title on Table 39 and Table 44.
Updated values of On-Chip Differential Termination resistors. Updated Table 7. Updated
configuration bitstream sizes for XC3S250E through XC3S1600E in Table 44, Table 50, Table 56, and
Table 59. Added DLL Performance Differences Between Steppings. Added Stepping 0
Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration. Added Stepping
0 limitations when Daisy-Chaining in SPI configuration mode. Added Multiplier/Block RAM
Interaction section. Updated Digital Clock Managers (DCMs) section, especially Phase Shifter
(PS) portion. Corrected and enhanced the clock infrastructure diagram in Figure 45 and Table 41.
Added CCLK Design Considerations section. Added Design Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins section. Added Spansion, Winbond, and Macronix to list of SPI Flash
vendors in Table 52 and Table 55. Clarified that SPI mode configuration supports Atmel ‘C’- and
‘D’-series DataFlash. Updated the Programming Support section for SPI Flash PROMs. Added
Power-On Precautions if PROM Supply is Last in Sequence, Compatible Flash Families, and
BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs sections to BPI
configuration mode topic. Updated and amplified Powering Spartan-3E FPGAs section. Added
Production Stepping section.
Upgraded data sheet status to Preliminary. Updated Input Delay Functions and Figure 6. Added
clarification that Input-only pins also have Pull-Up and Pull-Down Resistors. Added design note
about address setup and hold requirements to Block RAM. Added warning message about software
differences between ISE 8.1i, Service Pack 3 and earlier software to FIXED Phase Shift Mode and
VARIABLE Phase Shift Mode. Added message about using GCLK1 in DLL Clock Input
Connections and Clock Inputs. Updated Figure 45. Added additional information on HSWAP
behavior to Pin Behavior During Configuration. Highlighted which pins have configuration pull-up
resistors unaffected by HSWAP in Table 45. Updated bitstream image sizes for the XC3S1200E and
XC3S1600E in Table 44, Table 50, Table 56, and Table 59. Clarified that ‘B’-series Atmel DataFlash
SPI PROMs can be used in Commercial temperature range applications in Table 52 and Figure 54.
Updated Figure 56. Updated Dynamically Loading Multiple Configuration Images Using
MultiBoot Option section. Added design note about BPI daisy-chaining software support to BPI
Daisy-Chaining section. Updated JTAG revision codes in Table 66. Added No Internal Charge
Pumps or Free-Running Oscillators. Updated information on production stepping differences in
Table 70. Updated Software Version Requirements.
Updated JTAG User ID information. Clarified Note 1, Figure 5. Clarified that Figure 45 shows
electrical connectivity and corrected left- and right-edge DCM coordinates. Updated Table 30,
Table 31, and Table 32 to show the specific clock line driven by the associated BUFGMUX primitive.
Corrected the coordinate locations for the associated BUFGMUX primitives in Table 31 and Table 32.
Updated Table 41 to show that the I0-input is the preferred connection to a BUFGMUX.
Made further clarifying changes to Figure 46, showing both direct inputs to BUFGMUX primitives and
to DCMs. Added Atmel AT45DBxxxD-series DataFlash serial PROMs to Table 52. Added details that
intermediate FPGAs in a BPI-mode, multi-FPGA configuration daisy-chain must be from either the
Spartan-3E or the Virtex-5 FPGA families (see BPI Daisy-Chaining). Added Using JTAG Interface
to Communicate to a Configured FPGA Design. Minor updates to Figure 67 and Figure 68.
Clarified which Spartan-3E FPGA product options support the Readback feature, shown in Table 67.
Corrected various typos and incorrect links.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
115
Product Specification