XC3S100E_06 Datasheet, PDF (161/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Spartan-3E FPGA Family:
Pinout Descriptions
DS312-4 (v3.4) November 9, 2006
0 _{Product Specification}
Introduction
This section describes the various pins on a Spartan™-3E
FPGA and how they connect within the supported compo-
nent packages.
Pin Types
Most pins on a Spartan-3E FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 11 different
functional types of pins on Spartan-3E packages, as out-
lined in Table 123. In the package footprint drawings that fol-
low, the individual pins are color-coded according to pin
type as in the table.
Table 123: Types of Pins on Spartan-3E FPGAs
Type /
Color Code
Description
Pin Name(s) in Type
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to IO
form differential I/Os.
IO_Lxxy_#
INPUT
Unrestricted, general-purpose input-only pin. This pin does not have an output IP
structure.
IP_Lxxy_#
DUAL
Dual-purpose pin used in some configuration modes during the configuration
process and then usually available as a user I/O after configuration. If the pin is
not used during configuration, this pin behaves as an I/O-type pin. Some of the
dual-purpose pins are also shared with bottom-edge global (GCLK) or right-half
(RHCLK) clock inputs. See the Configuration section in Module 2 for additional
information on these signals.
M[2:0]
HSWAP
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
VREF
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all
other VREF pins in the same bank, provides a reference voltage input for certain
I/O standards. If used for a reference voltage within a bank, all VREF pins within
the bank must be connected.
IP/VREF_#
IP_Lxx_#/VREF_#
IO/VREF_#
IO_Lxx_#/VREF_#
CLK
Either a user-I/O pin or an input to a specific clock buffer driver. Every package IO_Lxx_#/GCLK[15:2],
has 16 global clock inputs that optionally clock the entire device. The RHCLK IP_Lxx_#/GCLK[1:0],
inputs optionally clock the right-half of the device. The LHCLK inputs optionally IO_Lxx_#/LHCLK[7:0],
clock the left-half of the device. Some of the clock pins are shared with the
IO_Lxx_#/RHCLK[7:0]
dual-purpose configuration pins and are considered DUAL-type. See the
Clocking Infrastructure section in Module 2 for additional information on these
signals.
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