XC3S100E_06 Datasheet, PDF (167/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Pinout Descriptions
VQ100: 100-lead Very-thin Quad Flat Package
The XC3S100E and the XC3S250E devices are available in
the 100-lead very-thin quad flat package, VQ100. Both
devices share a common footprint for this package as
shown in Table 130 and Figure 81.
Table 130 lists all the package pins. They are sorted by
bank number and then by pin name of the largest device.
Pins that form a differential I/O pair appear together in the
table. The table also shows the pin number for each pin and
the pin type, as defined earlier.
Table 130: VQ100 Package Pinout (Continued)
Bank
XC3S100E
XC3S250E
Pin Name
VQ100
Pin
Number
Type
1
IO_L03P_1/RHCLK0
P60
RHCLK
1
IO_L04N_1/RHCLK3
P63
RHCLK
1
IO_L04P_1/RHCLK2
P62
RHCLK
1
IO_L05N_1/RHCLK5
P66
RHCLK
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode. Conse-
quently, the VQ100 footprint has fewer DUAL-type pins
than other packages.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
1
IO_L05P_1/RHCLK4
1
IO_L06N_1/RHCLK7
1
IO_L06P_1/RHCLK6
1
IO_L07N_1
1
IO_L07P_1
1
IP/VREF_1
P65
RHCLK
P68
RHCLK
P67
RHCLK
P71
I/O
P70
I/O
P69
VREF
Pinout Table
Table 130 shows the pinout for production Spartan-3E
FPGAs in the VQ100 package.
Table 130: VQ100 Package Pinout
Bank
XC3S100E
XC3S250E
Pin Name
VQ100
Pin
Number
Type
0
IO
P92
I/O
0
IO_L01N_0
P79
I/O
0
IO_L01P_0
P78
I/O
0
IO_L02N_0/GCLK5
P84
GCLK
0
IO_L02P_0/GCLK4
P83
GCLK
0
IO_L03N_0/GCLK7
P86
GCLK
0
IO_L03P_0/GCLK6
P85
GCLK
0
IO_L05N_0/GCLK11
P91
GCLK
0
IO_L05P_0/GCLK10
P90
GCLK
0
IO_L06N_0/VREF_0
P95
VREF
0
IO_L06P_0
P94
I/O
0
IO_L07N_0/HSWAP
P99
DUAL
0
IO_L07P_0
P98
I/O
0
IP_L04N_0/GCLK9
P89
GCLK
0
IP_L04P_0/GCLK8
P88
GCLK
0
VCCO_0
P82
VCCO
0
VCCO_0
P97
VCCO
1
IO_L01N_1
P54
I/O
1
IO_L01P_1
P53
I/O
1
IO_L02N_1
P58
I/O
1
IO_L02P_1
P57
I/O
1
IO_L03N_1/RHCLK1
P61
RHCLK
1
VCCO_1
P55
VCCO
1
VCCO_1
P73
VCCO
2
IO/D5
P34
DUAL
2
IO/M1
P42
DUAL
2
IO_L01N_2/INIT_B
P25
DUAL
2
IO_L01P_2/CSO_B
P24
DUAL
2
IO_L02N_2/MOSI/CSI_B
P27
DUAL
2
IO_L02P_2/DOUT/BUSY
P26
DUAL
2
IO_L03N_2/D6/GCLK13
P33 DUAL/GCLK
2
IO_L03P_2/D7/GCLK12
P32 DUAL/GCLK
2
IO_L04N_2/D3/GCLK15
P36 DUAL/GCLK
2
IO_L04P_2/D4/GCLK14
P35 DUAL/GCLK
2
IO_L06N_2/D1/GCLK3
P41 DUAL/GCLK
2
IO_L06P_2/D2/GCLK2
P40 DUAL/GCLK
2
IO_L07N_2/DIN/D0
P44
DUAL
2
IO_L07P_2/M0
P43
DUAL
2
IO_L08N_2/VS1
P48
DUAL
2
IO_L08P_2/VS2
P47
DUAL
2
IO_L09N_2/CCLK
P50
DUAL
2
IO_L09P_2/VS0
P49
DUAL
2
IP/VREF_2
P30
VREF
2
IP_L05N_2/M2/GCLK1
P39 DUAL/GCLK
2
IP_L05P_2/RDWR_B/
GCLK0
P38 DUAL/GCLK
2
VCCO_2
P31
VCCO
2
VCCO_2
P45
VCCO
3
IO_L01N_3
P3
I/O
3
IO_L01P_3
P2
I/O
3
IO_L02N_3/VREF_3
P5
VREF
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
167
Product Specification