XC3S100E_06 Datasheet, PDF (228/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Pinout Descriptions
R
Table 153: FG484 Package Pinout (Continued)
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
VCCINT VCCINT
J10 VCCINT
VCCINT VCCINT
K9 VCCINT
VCCINT VCCINT
K11 VCCINT
VCCINT VCCINT
K13 VCCINT
VCCINT VCCINT
L10 VCCINT
VCCINT VCCINT
L11 VCCINT
VCCINT VCCINT
L12 VCCINT
VCCINT VCCINT
L14 VCCINT
VCCINT VCCINT
M9 VCCINT
Table 153: FG484 Package Pinout (Continued)
Bank
XC3S1600E
Pin Name
FG484
Ball
Type
VCCINT VCCINT
M11 VCCINT
VCCINT VCCINT
M12 VCCINT
VCCINT VCCINT
M13 VCCINT
VCCINT VCCINT
N10 VCCINT
VCCINT VCCINT
N12 VCCINT
VCCINT VCCINT
N14 VCCINT
VCCINT VCCINT
P13 VCCINT
User I/Os by Bank
Table 154 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG484 pack-
age.
Table 154: User I/Os Per Bank for the XC3S1600E in the FG484 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
94
56
22
1
7
Right
1
94
50
16
21
7
Bottom
2
94
45
18
24
7
Left
3
94
63
16
0
7
TOTAL
376
214
72
46
28
CLK
8
0⁽¹⁾
0⁽¹⁾
8
16
Notes:
1. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
228
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DS312-4 (v3.4) November 9, 2006
Product Specification