XC3S100E_06 Datasheet, PDF (84/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
Daisy-Chaining
DESIGN NOTE:
! ^{SPI mode daisy chains are supported only in}
Stepping 1 and later silicon versions.
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 57. Daisy-chaining from a single SPI
serial Flash PROM is supported in Stepping 1 and later
devices. It is not supported in Stepping 0 devices. Use SPI
Flash mode (M[2:0] = <0:0:1>) for the FPGA connected to
the Platform Flash PROM and Slave Serial mode
(M[2:0] = <1:1:1>) for all other FPGAs in the daisy-chain.
After the master FPGA—the FPGA on the left in the dia-
gram—finishes loading its configuration data from the SPI
Flash PROM, the master device uses its DOUT output pin
to supply data to the next device in the daisy-chain, on the
falling CCLK edge.
!
SPI-based daisy-chaining is
only supported in Stepping 1.
+1.2V
VCCINT
P
HSWAP
VCCO_0
SPI Mode
‘0’
M2
‘0’
M1
‘1’
M0
VCCO_2
MOSI
DIN
CSO_B
Variant Select
‘1’
S
‘1’
+2.5V
JTAG
TDI
TMS
TCK
TDO
Spartan-3E
VS2 _FPGA
VS1
VS0
CCLK
DOUT
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
I
+3.3V
+2.5V
W
‘1’
+3.3V
SPI
Serial
P
Flash
VCC
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
GND
+2.5V +3.3V
+1.2V
P
Slave
Serial
Mode
‘1’
‘1’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2
M1
M0
Spartan-3E
FPGA
VCCO_0
+3.3V
CCLK
DIN
TDI
TMS
TCK
DOUT
INIT_B
VCCAUX
TDO
PROG_B
GND
DONE
+2.5V
CCLK
DOUT
PROG_B
Recommend
open-drain
driver
PROG_B
TCK
TMS
DONE
INIT_B
Figure 57: Daisy-Chaining from SPI Flash Mode (Stepping 1 and Later)
DS312-2_48_103105
Programming Support
For successful daisy-chaining, the DONE_cycle configura-
tion option must be set to cycle 5 or sooner. The default
cycle is 4. See Table 68 and the Start-Up section for addi-
tional information.
I _{In production applications, the SPI Flash PROM is usu-}
ally pre-programmed before it is mounted on the printed cir-
cuit board. The Xilinx ISE development software produces
industry-standard programming files that can be used with
third-party gang programmers. Consult your specific SPI
Flash vendor for recommended production programming
solutions.
In-system programming support is available from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the SPI Flash signals,
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the SPI Flash, in high-impedance (Hi-Z). If the
HSWAP input is Low, the I/Os have pull-up resistors to the
V_CCO input on their respective I/O bank. The external pro-
gramming hardware then has direct access to the SPI Flash
pins. The programming access points are highlighted in the
gray box in Figure 53, Figure 54, and Figure 57.
Beginning with the Xilinx ISE 8.2i software release, the
iMPACT programming utility provides direct, in-system pro-
totype programming support for STMicro M25P-series SPI
serial Flash PROMs and the Atmel AT45DB-series Data
Flash PROMs using the Platform Cable USB, Xilinx Parallel
IV, or other compatible programming cable.
84
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DS312-2 (v3.4) November 9, 2006
Product Specification