XC3S100E_06 Datasheet, PDF (165/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Pinout Descriptions
Table 128: Maximum User I/O by Package
Device
Maximum
All Possible I/Os by Type
User I/Os Maximum Maximum
and
Input- Differential
Package Input-Only Only
Pairs
I/O INPUT DUAL VREF CLK⁽¹⁾ N.C.
XC3S100E
66
7
30
16
1
21
4
24
0
VQ100
XC3S250E
66
7
30
16
1
21
4
24
0
XC3S100E
83
11
35
16
2
42
7
16
9
XC3S250E CP132
92
7
41
22
0
46
8
16
0
XC3S500E
92
7
41
22
0
46
8
16
0
XC3S100E
108
28
TQ144
XC3S250E
108
28
40
22
19
42
9
16
0
40
20
21
42
9
16
0
XC3S250E
158
32
PQ208
XC3S500E
158
32
65
58
25
46
13
16
0
65
58
25
46
13
16
0
XC3S250E
172
40
68
62
33
46
15
16
16
XC3S500E FT256
190
41
77
76
33
46
19
16
0
XC3S1200E
190
40
77
78
31
46
19
16
0
XC3S500E
232
56
92
102 48
46
20
16
18
XC3S1200E FG320
250
56
99
120 47
46
21
16
0
XC3S1600E
250
56
99
120 47
46
21
16
0
XC3S1200E
304
72
124
156 62
46
24
16
0
FG400
XC3S1600E
304
72
124
156 62
46
24
16
0
XC3S1600E FG484
376
82
156
214 72
46
28
16
0
Notes:
1. All devices have 24 possible global clock and right- and left-half side clock inputs. The right-half and bottom-edge clock pins have shared
functionality in some FPGA configuration modes. Consequently, some clock pins are counted in the DUAL column.
Electronic versions of the package pinout tables and foot-
prints are available for download from the Xilinx website.
Download the files from the following location: Using a
spreadsheet program, the data can be sorted and reformat-
ted according to any specific needs. Similarly, the
ASCII-text file is easily parsed by most scripting programs.
http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
DS312-4 (v3.4) November 9, 2006
www.xilinx.com
165
Product Specification