XC3S100E_06 Datasheet, PDF (101/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
Intelligent V
Download Host
Configuration
Memory
Source
• Internal memory
• Disk drive
••
Over
Over
network
RF link
VCC
CLOCK
SERIAL_OUT
PROG_B
DONE
INIT_B
GND
••
•
Microcontroller
Processor
Tester
• Computer
+1.2V
P
Slave
Serial
Mode
‘1’
‘1’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2
M1
M0
Spartan-3E
CCLK FPGA
DIN
DOUT
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
DONE
GND
VCCO_0
V
V
+2.5V
+2.5V
+1.2V
P
Slave
Serial
Mode
‘1’
‘1’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2
M1
M0
Spartan-3E
CCLK FPGA
DIN
DOUT
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
VCCO_2
+2.5V
CCLK
DOUT
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
Figure 64: Daisy-Chaining using Slave Serial Mode
PROG_B
DONE
INIT_B
TMS
TCK
DS312-2_55_102105
JTAG Mode
The Spartan-3E FPGA has a dedicated four-wire IEEE
1149.1/1532 JTAG port that is always available any time the
FPGA is powered and regardless of the mode pin settings.
However, when the FPGA mode pins are set for JTAG
mode (M[2:0] = <1:0:1>), the FPGA waits to be configured
via the JTAG port after a power-on event or when PROG_B
is asserted. Selecting the JTAG mode simply disables the
other configuration modes. No other pins are required as
part of the configuration interface.
Figure 65 illustrates a JTAG-only configuration interface.
The JTAG interface is easily cascaded to any number of
FPGAs by connecting the TDO output of one device to the
TDI input of the next device in the chain. The TDO output of
the last device in the chain loops back to the port connector.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
101
Product Specification