XC3S100E_06 Datasheet, PDF (70/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
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Table 46: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
Pin(s)
I/O Standard
Output Drive
All, including CCLK
LVCMOS25
8 mA
Slew Rate
Slow
Table 46 shows the default I/O standard setting for the vari-
ous configuration pins during the configuration process. The
configuration interface is designed primarily for 2.5V opera-
tion when the VCCO_2 (and VCCO_1 in BPI mode) con-
nects to 2.5V.
The configuration pins also operate at other voltages by set-
ting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or
1.8V. The change on the V_CCO supply also changes the I/O
drive characteristics. For example, with V_CCO = 3.3V, the
output current when driving High, I_OH, increases to approx-
imately 12 to 16 mA, while the current when driving Low,
I_OL, remains 8 mA. At V_CCO = 1.8V, the output current when
driving High, I_OH, decreases slightly to approximately 6 to 8
mA. Again, the current when driving Low, I_OL, remains
8 mA.
CCLK Design Considerations
The FPGA’s configuration process is controlled by the
CCLK configuration clock. Consequently, signal integrity of
CCLK is important to guarantee successful configuration.
Poor CCLK signal integrity caused by ringing or reflections
might cause double-clocking, causing the configuration pro-
cess to fail.
Although the CCLK frequency is relatively low, Spartan-3E
FPGA output edge rates are fast. Therefore, careful atten-
tion must be paid to the CCLK signal integrity on the printed
circuit board. Signal integrity simulation with IBIS is recom-
mended. For all configuration modes except JTAG, the sig-
nal integrity must be considered at every CCLK trace
destination, including the FPGA’s CCLK pin.
This analysis is especially important when the FPGA
re-uses the CCLK pin as a user-I/O after configuration. In
these cases, there might be unrelated devices attached to
CCLK, which add additional trace length and signal destina-
tions.
In the Master Serial, SPI, and BPI configuration modes, the
FPGA drives the CCLK pin and CCLK should be treated as
a full bidirectional I/O pin for signal integrity analysis. In BPI
mode, CCLK is only used in multi-FPGA daisy-chains.
The best signal integrity is ensured by following these basic
PCB guidelines:
• Route the CCLK signal as a 50 Ω
controlled-impedance transmission line.
• Route the CCLK signal without any branching. Do not
use a “star” topology.
• Keep stubs, if required, shorter than 10 mm (0.4
inches).
• Terminate the end of the CCLK transmission line.
Design Considerations for the HSWAP,
M[2:0], and VS[2:0] Pins
Unlike previous Spartan FPGA families, nearly all of the
Spartan-3E dual-purpose configuration pins are available
as full-featured user I/O pins after successful configuration,
when the DONE output goes High.
The HSWAP pin, the mode select pins (M[2:0]), and the
variant-select pins (VS[2:0]) must have valid and stable
logic values at the start of configuration. VS[2:0] are only
used in the SPI configuration mode. The levels on the
M[2:0] pins and VS[2:0] pins are sampled when the INIT_B
pin returns High. See Figure 77 for a timing example.
The HSWAP pin defines whether FPGA user I/O pins have
a pull-up resistor connected to their associated V_CCO sup-
ply pin during configuration or not, as shown Table 47.
HSWAP must be valid at the start of configuration and
remain constant throughout the configuration process.
Table 47: HSWAP Behavior
HSWAP
Value
Description
0
Pull-up resistors connect to the associated
V_CCO supply for all user-I/O or dual-purpose
I/O pins during configuration. Pull-up resistors
are active until configuration completes.
1
Pull-up resistors disabled during configuration.
All user-I/O or dual-purpose I/O pins are in a
high-impedance state.
The Configuration section provides detailed schematics for
each configuration mode. The schematics indicate the
required logic values for HSWAP, M[2:0], and VS[2:0] but
do not specify how the application provides the logic Low or
High value. The HSWAP, M[2:0], and VS[2:0] pins can be
either dedicated or reused by the FPGA application.
Dedicating the HSWAP, M[2:0], and VS[2:0] Pins
If the HSWAP, M[2:0], and VS[2:0] pins are not required by
the FPGA design after configuration, simply connect these
pins directly to the V_CCO or GND supply rail shown in the
appropriate configuration schematic.
Reusing HSWAP, M[2:0], and VS[2:0] After Config-
uration
To reuse the HSWAP, M[2:0], and VS[2:0] pin after configu-
ration, use pull-up or pull-down resistors to define the logic
values shown in the appropriate configuration schematic.
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DS312-2 (v3.4) November 9, 2006
Product Specification