XC3S100E_06 Datasheet, PDF (24/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
The SLICEM pair supports two additional functions:
• Two 16x1 distributed RAM blocks, RAM16
• Two 16-bit shift registers, SRL16
Each of these elements is described in more detail in the fol-
lowing sections.
Logic Cells
The combination of a LUT and a storage element is known
as a “Logic Cell”. The additional features in a slice, such as
the wide multiplexers, carry logic, and arithmetic gates, add
to the capacity of a slice, implementing logic that would oth-
erwise require additional LUTs. Benchmarks have shown
that the overall slice is equivalent to 2.25 simple logic cells.
This calculation provides the equivalent logic cell count
shown in Table 9.
Slice Details
Figure 15 is a detailed diagram of the SLICEM. It represents
a superset of the elements and connections to be found in
all slices. The dashed and gray lines (blue when viewed in
color) indicate the resources found only in the SLICEM and
not in the SLICEL.
Each slice has two halves, which are differentiated as top
and bottom to keep them distinct from the upper and lower
slices in a CLB. The control inputs for the clock (CLK), Clock
Enable (CE), Slice Write Enable (SLICEWE1), and
Reset/Set (RS) are shared in common between the two
halves.
The LUTs located in the top and bottom portions of the slice
are referred to as "G" and "F", respectively, or the "G-LUT"
and the "F-LUT". The storage elements in the top and bot-
tom portions of the slice are called FFY and FFX, respec-
tively.
Each slice has two multiplexers with F5MUX in the bottom
portion of the slice and FiMUX in the top portion. Depending
on the slice, the FiMUX takes on the name F6MUX,
F7MUX, or F8MUX, according to its position in the multi-
plexer chain. The lower SLICEL and SLICEM both have an
F6MUX. The upper SLICEM has an F7MUX, and the upper
SLICEL has an F8MUX.
The carry chain enters the bottom of the slice as CIN and
exits at the top as COUT. Five multiplexers control the chain:
CYINIT, CY0F, and CYMUXF in the bottom portion and
CY0G and CYMUXG in the top portion. The dedicated arith-
metic logic includes the exclusive-OR gates XORF and
XORG (bottom and top portions of the slice, respectively)
as well as the AND gates FAND and GAND (bottom and top
portions, respectively).
See Table 10 for a description of all the slice input and out-
put signals.
Table 10: Slice Inputs and Outputs
Name
Location
Direction
Description
F[4:1]
SLICEL/M Bottom
Input F-LUT and FAND inputs
G[4:1]
SLICEL/M Top
Input G-LUT and GAND inputs or Write Address (SLICEM)
BX
SLICEL/M Bottom
Input Bypass to or output (SLICEM) or storage element, or control input to
F5MUX, input to carry logic, or data input to RAM (SLICEM)
BY
SLICEL/M Top
Input
Bypass to or output (SLICEM) or storage element, or control input to
FiMUX, input to carry logic, or data input to RAM (SLICEM)
BXOUT
SLICEM Bottom
Output BX bypass output
BYOUT
SLICEM Top
Output BY bypass output
ALTDIG
SLICEM Top
Input Alternate data input to RAM
DIG
SLICEM Top
Output ALTDIG or SHIFTIN bypass output
SLICEWE1 SLICEM Common
Input RAM Write Enable
F5
SLICEL/M Bottom
Output Output from F5MUX; direct feedback to FiMUX
FXINA
SLICEL/M Top
Input Input to FiMUX; direct feedback from F5MUX or another FiMUX
FXINB
SLICEL/M Top
Input Input to FiMUX; direct feedback from F5MUX or another FiMUX
Fi
SLICEL/M Top
Output Output from FiMUX; direct feedback to another FiMUX
CE
SLICEL/M Common
Input FFX/Y Clock Enable
SR
SLICEL/M Common
Input FFX/Y Set or Reset or RAM Write Enable (SLICEM)
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DS312-2 (v3.4) November 9, 2006
Product Specification