XC3S100E_06 Datasheet, PDF (196/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Pinout Descriptions
R
Table 142: FT256 Package Pinout (Continued)
Bank
3
XC3S250E Pin Name
N.C. (‹)
XC3S500E Pin Name
IO_L17N_3
XC3S1200E Pin Name
IO_L17N_3
3
N.C. (‹)
IO_L17P_3
IO_L17P_3
3
IO_L18N_3
3
IO_L18P_3
3
IO_L19N_3
3
IO_L19P_3
3
IP
3
IP
3
IO
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
IP
IO
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IP
IP
IP
3
IP
3
IP
3
IP
3
IP
3
IP
3
IP/VREF_3
3
IO/VREF_3
IP
IP
IP
IP
IP
IP/VREF_3
IO/VREF_3
IP
IP
IP
IP
IP
IP/VREF_3
IP/VREF_3
3
3
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FT256
Ball
L4
M4
P1
P2
R1
R2
D2
F2
F5
H1
J6
K4
M3
N3
G1
N2
E2
G6
K6
M2
A1
A16
B9
F6
F11
G7
G8
G9
G10
H2
H7
H8
H9
Type
250E: N.C.
500E: I/O
1200E: I/O
250E: N.C.
500E: I/O
1200E: I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
250E: I/O
500E: I/O
1200E: INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
VREF
250E: VREF(I/O)
500E: VREF(I/O)
1200E:
VREF(INPUT)
VCCO
VCCO
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
196
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DS312-4 (v3.4) November 9, 2006
Product Specification