XC3S100E_06 Datasheet, PDF (11/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Input Delay Functions
Each IOB has a programmable delay block that optionally
delays the input signal from 0 to approximately 5.8 ns. In
Figure 6, the signal is first delayed by an initial delay of
either 0 or approximately 1 to 3 ns. The range depends on
the specific Spartan-3E FPGA array used. The initial delay
then feeds a 7-tap delay line. This delay line has an approx-
imate value of 250 ps per tap, again somewhat architecture
dependent. All seven taps are available via a multiplexer for
use as an asynchronous input directly into the FPGA fabric.
In this way, the delay is programmable from 0 to ~5.8 ns in
~250 ps steps. Three of the seven taps are also available
via a multiplexer to the D inputs of the synchronous storage
elements. The delay inserted in the path to the storage ele-
ment can be varied from 0 to ~5.8 ns in ~500 ps steps. The
first, coarse delay element is common to both asynchro-
nous and synchronous paths, and must be either used or
not used for both paths.
The delay values are set up in the silicon once at configura-
tion time—they are non-modifiable in device operation.
The primary use for the input delay element is to adjust the
input delay path to ensure that there is no hold time require-
ment when using the input flip-flop(s) with a global clock.
The default value is chosen automatically by the Xilinx soft-
ware tools as the value depends on device size and the spe-
cific device edge where the flip-flop resides. The value set
by the Xilinx ISE software and the resulting effects on input
timing are reported using the Timing Analyzer tool.
If the design uses a DCM in the clock path, then the delay
element can be safely set to zero because the
Delay-Locked Loop (DLL) compensation automatically
ensures that there is still no input hold time requirement.
Both asynchronous and synchronous values can be modi-
fied, which is useful where extra delay is required on clock
or data inputs, for example, in interfaces to various types of
RAM.
IFD_DELAY_VALUE
Synchronous input (IQ1)
DQ
Synchronous input (IQ2)
DQ
Initial Delay
PAD
Asynchronous input (I)
IBUF_DELAY_VALUE
DS312-2_18_102306
Figure 6: Programmable Fixed Input Delay Elements
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
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Product Specification