XC3S100E_06 Datasheet, PDF (79/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 53: Example SPI Flash PROM Connections and Pin Naming
SPI Flash Pin
FPGA Connection
DATA_IN
MOSI
DATA_OUT
DIN
SELECT
CSO_B
CLOCK
CCLK
WR_PROTECT
W
Not required for FPGA configuration. Must be
High to program SPI Flash. Optional
connection to FPGA user I/O after
configuration.
HOLD
(see Figure 53)
Not required for FPGA configuration but must
be High during configuration. Optional
connection to FPGA user I/O after
configuration. Not applicable to Atmel
DataFlash.
RESET
(see Figure 54)
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
High during configuration. Optional
connection to FPGA user I/O after
configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
RDY/BUSY
(see Figure 54)
Only applicable to Atmel DataFlash and only
available on certain packages. Not required
for FPGA configuration. Output from
DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
STMicro
D
Q
S
C
W
HOLD
N/A
N/A
Silicon
Storage
NexFlash Technology
DI
SI
DO
SO
CS
CE#
CLK
SCK
WP
WP#
HOLD
HOLD#
N/A
N/A
N/A
N/A
Atmel
DataFlash
SI
SO
CS
SCK
WP
N/A
RESET
RDY/BUSY
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
P ^{Similarly, the FPGA’s HSWAP pin must be Low to}
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
79
Product Specification