XC3S100E_06 Datasheet, PDF (41/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

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Functional Description
Table 25: Block RAM Function Table (Continued)
Input Signals
Output Signals
RAM Data
GSR EN SSR WE CLK ADDR DIP DI
DOP
DO
Parity
Data
Write RAM, Simultaneous Read Operation
0
1
0
1↑
addr pdata Data
WRITE_MODE = WRITE_FIRST
pdata
data
RAM(addr) RAM(addr)
← pdata
← data
WRITE_MODE = READ_FIRST
RAM(data) RAM(data) RAM(addr) RAM(addr)
← pdata
← pdata
WRITE_MODE = NO_CHANGE
No Chg
No Chg
RAM(addr) RAM(addr)
← pdata
← pdata
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a output latch to the DO
outputs. The timing for basic data access is shown in the
portions of Figure 33, Figure 34, and Figure 35 during
which WE is Low.
Data also can be accessed on the DO outputs when assert-
ing the WE input based on the value of the WRITE_MODE
attribute as described in Table 26.
Table 26: WRITE_MODE Effect on Data Output Latches During Write Operations
Write Mode
Effect on Same Port
Effect on Opposite Port
(dual-port only with same address)
WRITE_FIRST
Read After Write
Data on DI and DIP inputs is written into
specified RAM location and simultaneously
appears on DO and DOP outputs.
Invalidates data on DO and DOP outputs.
READ_FIRST
Read Before Write
Data from specified RAM location appears on
DO and DOP outputs.
Data on DI and DIP inputs is written into
specified location.
Data from specified RAM location appears on
DO and DOP outputs.
NO_CHANGE
No Read on Write
Data on DO and DOP outputs remains
unchanged.
Data on DI and DIP inputs is written into
specified location.
Invalidates data on DO and DOP outputs.
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
41
Product Specification