XC3S100E_06 Datasheet, PDF (148/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Miscellaneous DCM Timing
Table 109: Miscellaneous DCM Timing
Symbol
Description
Min
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
DCM_RST_PW_MAX⁽²⁾
Maximum duration of a RST pulse width
N/A
N/A
DCM_CONFIG_LAG_TIME⁽³⁾ Maximum duration from V_CCINT applied to FPGA
N/A
configuration successfully completed (DONE pin goes
High) and clocks applied to DCM DLL
N/A
Max
Units
-
CLKIN
cycles
N/A seconds
N/A seconds
N/A minutes
N/A minutes
Notes:
1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
2. This specification is equivalent to the Virtex-4 DCM_RESET specfication.This specification does not apply for Spartan-3E FPGAs.
3. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs.
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DS312-3 (v3.4) November 9, 2006
Product Specification