XC3S100E_06 Datasheet, PDF (129/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
DC and Switching Characteristics
Table 87: Setup and Hold Times for the IOB Input Path
Symbol
Description
Setup Times
T_IOPICK
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop
(IFF). No Input Delay is
programmed.
T_IOPICKD
Time from the setup of data at the
Input pin to the active transition at the
IFF’s ICLK input. The Input Delay is
programmed.
Hold Times
T_IOICKP
Time from the active transition at the
IFF’s ICLK input to the point where
data must be held at the Input pin. No
Input Delay is programmed.
T_IOICKPD
Time from the active transition at the
IFF’s ICLK input to the point where
data must be held at the Input pin.
The Input Delay is programmed.
Set/Reset Pulse Width
T_{RPW_IOB} Minimum pulse width to SR control
input on IOB
Conditions
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE = 0
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE =
default software setting
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE = 0
LVCMOS25⁽²⁾,
IFD_DELAY_VALUE =
default software setting
IFD_
DELAY_
VALUE=
0
2
3
0
2
3
Device
All
XC3S100E
All Others
All
XC3S100E
All Others
All
Speed Grade
-5
-4
Min
Min
Units
1.84
2.12
ns
6.12
7.01
ns
6.76
7.72
–0.76 –0.76 ns
–3.74 –3.74 ns
–4.32 –4.32
1.00
1.15
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 94 and are based on the operating conditions set forth in
Table 76 and Table 79.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 90.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 90. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 88: Sample Window (Source Synchronous)
Symbol
Description
Max
T_SAMP
Setup and hold capture window of
an IOB input flip-flop.
The input capture sample window value is highly specific to a
particular application, device, package, I/O standard, I/O
placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx application note for application-specific
values.
• XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at
Speeds Up to 666 Mbps
www.xilinx.com/bvdocs/appnotes/xapp485.pdf
Units
ps
DS312-3 (v3.4) November 9, 2006
www.xilinx.com
129
Product Specification