XC3S100E_06 Datasheet, PDF (15/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

R
Functional Description
D1
From
Fabric
D2
DQ
DQ
SelectIO Signal Standards
PAD
The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards (Table 6 and
Table 7). The majority of the I/Os also can be used to form
differential pairs to support any of the differential signaling
standards (Table 7).
OCLK1
OCLK2
OCLK1
OCLK2
D1 d
d+2
d+4
d+6
d+8 d+10
D2 d+1
d+3
d+5
d+7
d+9
PAD
d d+1 d+2 d+3 d+4 d+5 d+6 d+7 ^d+8
DS312-2_23_030105
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to “Entry Strategies for Xilinx Con-
straints” in the Xilinx Software Manuals and Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. For a
particular V_CCO voltage, Table 6 and Table 7 list all of the
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.
Figure 10: Output DDR
Table 6: Single-Ended IOSTANDARD Bank Compatibility
Single-Ended
IOSTANDARD
LVTTL
1.2V
-
V_CCO Supply/Compatibility
1.5V
-
1.8V
-
2.5V
-
3.3V
Input/
Output
Input Requirements
V_REF
Board
Termination
Voltage (V_TT)
N/R⁽¹⁾
N/R
LVCMOS33
-
-
-
-
Input/
Output
N/R
N/R
LVCMOS25
-
-
-
Input/
Output
Input
N/R
N/R
LVCMOS18
-
-
Input/
Output
Input
Input
N/R
N/R
LVCMOS15
-
Input/
Output
Input
Input
Input
N/R
N/R
LVCMOS12
Input/
Output
Input
Input
Input
Input
N/R⁽¹⁾
N/R
PCI33_3
-
-
-
-
Input/
Output
N/R
N/R
PCI66_3
-
-
-
-
Input/
Output
N/R
N/R
PCIX
Input/
Output
N/R
N/R
HSTL_I_18
-
-
Input/
Output
Input
Input
0.9
0.9
DS312-2 (v3.4) November 9, 2006
www.xilinx.com
15
Product Specification