XC3S100E_06 Datasheet, PDF (102/231 Pages) Xilinx, Inc – Configurable Logic Block (CLB)

Functional Description
R
+1.2V
+1.2V
P
JTAG
Mode
‘1’
‘0’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2 _Spartan-3E
M1
FPGA
M0
TDI
TMS
TCK
VCCAUX
TDO
VCCO_0
VCCO_2
+2.5V
P
JTAG
Mode
‘1’
‘0’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2 _Spartan-3E
M1
FPGA
M0
TDI
TMS
TCK
VCCAUX
TDO
VCCO_0
VCCO_2
+2.5V
+2.5V
JTAG
TDI
TMS
TCK
TDO
PROG_B
DONE
GND
PROG_B
GND
DONE
Figure 65: JTAG Configuration Mode
TMS
TCK
DS312-2_56_021405
Voltage Compatibility
The 2.5V V_CCAUX supply powers the JTAG interface. All of
the user I/Os are separately powered by their respective
VCCO_# supplies.
When connecting the Spartan-3E JTAG port to a 3.3V inter-
face, the JTAG input pins must be current-limited to 10 mA
or less using series resistors. Similarly, the TDO pin is a
CMOS output powered from +2.5V. The TDO output can
directly drive a 3.3V input but with reduced noise immunity.
See XAPP453: The 3.3V Configuration of Spartan-3 FPGAs
for additional information.
Table 66: Spartan-3E JTAG Device Identifiers
Spartan-3E
FPGA
4-Bit Revision Code
Step 0 Step 1
28-Bit
Vendor/Device
Identifier
XC3S100E
0x0
0x1
0x1C 10 093
XC3S250E
0x0
0x1
0x1C 1A 093
XC3S500E
0x0
0x2
0x4
0x1C 22 093
XC3S1200E
0x0
0x1
0x2
0x1C 2E 093
XC3S1600E
0x0
0x1
0x2
0x1C 3A 093
JTAG Device ID
Each Spartan-3E FPGA array type has a 32-bit device-spe-
cific JTAG device identifier as shown in Table 66. The lower
28 bits represent the device vendor (Xilinx) and device iden-
tifer. The upper four bits, ignored by most tools, represent
the revision level of the silicon mounted on the printed cir-
cuit board. Table 66 associates the revision code with a
specific stepping level.
JTAG User ID
The Spartan-3E JTAG interface also provides the option to
store a 32-bit User ID, loaded during configuration. The
User ID value is specified via the UserID configuration bit-
stream option, shown in Table 68, page 108.
Using JTAG Interface to Communicate to a
Configured FPGA Design
After the FPGA is configured, using any of the available
modes, the JTAG interface offers a possible communica-
tions channel to internal FPGA logic. The
BSCAN_SPARTAN3 design primitive provides two private
JTAG instructions to create an internal boundary scan
chain.
Maximum Bitstream Size for Daisy-Chains
The maximum bitstream length supported by Spartan-3E
FPGAs in serial daisy-chains is 4,294,967,264 bits
102
www.xilinx.com
DS312-2 (v3.4) November 9, 2006
Product Specification